Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-04-06
2004-04-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000
Reexamination Certificate
active
06721914
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of fault diagnosis; more specifically, it relates to a method for diagnosis of points of failure in complex electronic devices such as combinational logic circuits.
BACKGROUND OF THE INVENTION
When an integrated circuit (IC) fails one or more tests, it is of great interest to determine what caused the failure. Such a root cause analysis can point to unexpected and unwanted design sensitivities, to process deficiencies, or to the undesirable but usually unavoidable presence of random defects. In the first two cases, the failure diagnosis is used to drive a change in the design or the process, in the latter, information is used to improve manufacturing yield projections.
Standard techniques exist to analyze the data collected during test, and to derive locations of the defects in the IC. The general approach is to construct a set of potential defects that could explain the observed fail data, translate those defects into logic faults that can be simulated on a fault simulator, simulate all the faults in the list and then compare the simulated results against the data that is collected at the tester. The logic faults that match the test data most closely are assumed to correspond to the real defect.
Even though this approach is relatively successful, there are several problems that are rapidly becoming more apparent with decreasing feature sizes, and with increasingly aggressive design styles that deviate more and more from the robustly digital behavior assumed by logic simulators. The most serious one of those problems is that, in practice, only single stuck-at faults are used. Stuck-at fault models are suitable for logic simulation and they can be efficient in uncovering defects, even when those defects do not themselves correspond to stuck-at faults.
A stuck-at 0/stuck-at 1 models a defect that affects a single node by forcing the logical value at that node to be a zero or a one. Stuck-at faults are very restrictive as models of defects because they assume the defect influences only one node, is active all the time and behaves in one particular way. Using combinations of stuck-at faults removes the first of these drawbacks, but does little to alleviate the others. For example, bridging and intermittent defects cannot be modeled by any combination of stuck-at faults.
The problem in logic diagnostics is how to model real defects by logical abstractions that faithfully mimic the behavior of the defect, but that can also be simulated efficiently by diagnostic simulators.
Terms and Definitions
Circuit elements are gates or latches and define logic blocks. Each logic block has input pins and output pins. Blocks are connected to nets by pins. Often a net is referred to by the output pin number of the feeding logic block. A test pattern is a vector of 0′s and 1′s that is applied to the input of the first logic block(s) of a set of combinational logic blocks. After progressing through the set of combinational logic blocks the pattern that appears on the output pin of the last logic block(s) of the set of combinational logic blocks is either an expected pattern (a pass pattern) or an un-expected pattern (a fail pattern.) A fault (or logic fault) is a model of the defect causing the fail pattern. Whenever node is used hereafter, it may be read as pin or as net, depending upon the software package employed to do fault diagnostics. Stuck-at faults in particular are logical models of defects that affect a single node and that force a value on the node. Diagnostics tries to determine what type of fault on what nodes(s) of the set of combinational logic blocks would explain the fail pattern.
SUMMARY OF THE INVENTION
The approach to logic diagnosis of the present invention is based on the following: a defect is known to be active only when the IC fails a test pattern. When an IC fails a test pattern, the defect that caused the fail behaves as if it were a collection of one or more stuck-at faults, the set of stuck-at faults being unique for that test pattern both in their location (pins) and their polarities. The present invention identifies the minimum set of nodes that could be affected by the defect.
A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.
A second aspect of the present invention is a method for diagnosing defects in an integrated circuit comprising:(a) providing a set of failing test patterns and a set of main faults; (b) selecting a failing test pattern from the set of failing patterns; (c) creating one or more single-stuck at fault target faults and adding the target faults to a set of target faults; (d) selecting a target fault from the set of target faults; (e) simulating the selected target fault against a fault machine to create a simulated fail pattern; (f) comparing the simulated fail pattern to the selected fail pattern; (g) if the simulated fail pattern matches the selected failing pattern, adding the selected target fault to a explaining node list otherwise going to step (h); (h) repeating steps (d) through (g) until all target faults in the set of target faults have been selected; (i) repeating steps (b) through (h) until all failing test patterns in the set of failing test patterns have been selected; (j) selecting in turn, each simulated fault from the fault list, determining the associated nodes and creating sets of nodes; and (k) selecting a first set of sets of nodes such that each the simulated fail pattern matching a selected failing pattern could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.
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Bartenstein Thomas W.
Heaberlin Douglas C.
Huisman Leendert M.
Abraham Esaw
De'cady Albert
Schmeiser Olsen & Watts
Walsh Robert A.
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