Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-03-12
2003-11-25
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230010, C365S226000, C327S536000, C327S154000
Reexamination Certificate
active
06654296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of generating individualized voltages in semiconductor memory devices, and more specifically to devices, circuits and methods for generating dual voltages with a single charge pump in such devices.
2. Description of the Related Art
Semiconductor memory devices store data in memory cells, and use wordlines for addressing these cells. It is often advantageous to apply voltages to these components. For example, a backbiasing voltage applied to a p-well that surrounds a memory cell prevents erasure of the data stored in that cell. Indeed, such a voltage helps maintain a pn junction at a reverse biased state.
This problem was addressed in the prior art by using a single voltage generator for diverse needs. This, however, introduced pumping inefficiencies, since the applied voltages were best applied at different optimum values. The generated voltage was generally different than the individual optimum values.
Another solution was to include many voltage generators, one for each one of the required values. The problem, however, with that practice is that these voltage generators require a large area in the chip.
Referring now to
FIG. 1
, a prior art device
100
is shown as taught in U.S. Pat. No. 5,886,932. As will be appreciated, progress was made both in conserving space and in pumping efficiency, but only for generating different voltages, but only at different times.
Device
100
includes a VBB generator
110
that outputs a single back bias voltage. The output voltage can assume only one of two values, namely VBB
1
and VBB
2
, in two separate situations. In the first situation, a normal refresh mode is indicated, by using control signal NORM to activate a switch N
1
. In the second situation, a self refresh mode is indicated by using control signal SREF to activate a switch N
2
. In each case, an enable signal (ENABLE-N or ENABLE-S) is transmitted to VBB generator
110
. In turn, the latter returns the output to a level detector (Level Detector#1
120
or Level Detector#2
130
), for comparing with a respective reference voltage level, and controlling accordingly. This way the output voltage assumes the value of one of the reference voltage levels, as controlled by enable signals ENABLE-N or ENABLE-S.
Device
100
works where there is no requirement for simultaneous generation of different voltages. But it does not work where different voltages must be output concurrently.
Referring now to
FIG. 2
, another prior art device
200
is shown, which is taught in U.S. Pat. No. 5,889,664. As will be appreciated, progress was made in producing two voltages concurrently, and saving some space over the prior usual practice.
In device
200
, a single oscillator
210
is shared, which decreases the requirement for space. But there are two charge pumping circuits
220
,
230
, which still require a lot of area from device
200
. Circuits
220
,
230
receive signals S
212
, S
213
from oscillator
210
, and respectively generate voltages VBB, VPP. Voltage VBB is negative, while voltage VPP is positive, having higher voltage than supply voltage. Voltages VBB, VPP are sensed in detectors
240
,
250
respectively. These produce detection signals S
242
, S
252
for oscillator
210
, and detection signals S
246
, S
256
for a control logic unit
260
.
Referring now to
FIG. 3
, yet another prior art device
300
is shown. Device
300
makes additional progress in the prior art, but wastes electrical current.
Device
300
includes a single VBB
2
generator
310
, which may be made by a charge pump and a capacitor. Generator
310
generates a voltage VBB
2
at a node
320
, which is applied to a substrate of memory cell transistors
330
of a memory device in order to back bias it. In addition, a voltage VBB
1
is derived from node
320
by using a transistor
340
and a differential amplifier
350
. Amplifier
350
has a negative input at a reference value of the desired other voltage, namely VBB
1
. This produces a voltage VBB
1
that is applied to wordline driver circuits
360
of a memory device. Given the connections, voltage VBB
1
is higher than VBB
2
.
The problems with device
300
are associated with the generation of VBB
1
from node
320
. While differential amplifier
350
attempts to maintain the output at the desired level, it consumes a lot of electrical current. That is because transistor
340
drains current from node
370
. Accordingly, there is a decreased pumping efficiency, because of producing more VBB
2
voltage having low efficiency for maintaining the desired VBB
1
voltage level.
As semiconductor memory devices become smaller, it is required of them to have less area for components such as voltage generators. As they are to operate with less power, higher pumping efficiencies are needed.
BRIEF SUMMARY OF THE INVENTION
The present invention overcomes these problems and limitations of the prior art.
Generally, the present invention provides devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. These components may be a wordline driver circuit, a bit line sense amplifier block control circuit, a substrate of a memory cell transistor, etc.
An oscillator generates an oscillating signal, and a charge pump generates a pumping voltage responsive to the oscillating signal. A first switching circuit outputs from the pumping voltage a first voltage to the first component. A second switching circuit outputs from the pumping voltage a second voltage to the second component.
The switching circuits are optionally and preferably adjusted to deliver the first and second voltages at exactly the optimum values. This optimizes efficiency, and prevents waste in electrical current.
In addition, a single charge pump is used. This offers the advantage that space is conserved.
These and other features and advantages of the invention will become more readily apparent from the following Detailed Description, which proceeds with reference to the drawings, in which:
REFERENCES:
patent: 5589793 (1996-12-01), Kassapian
patent: 5726944 (1998-03-01), Pelley, III et al.
patent: 5886932 (1999-03-01), Choi
patent: 5889664 (1999-03-01), Oh
patent: 6166982 (2000-12-01), Murray et al.
patent: 6429732 (2002-08-01), Tedrow et al.
Jang Seong-jin
Jun Young-hyun
Lebentritt Michael S.
Luu Pho
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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