Device with integrated bipolar and MOSFET transistors in an...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S578000, C257S587000, C438S206000, C438S356000

Reexamination Certificate

active

06441446

ABSTRACT:

TECHNICAL FIELD
The present invention relates to monolithic integrated semiconductor structures and, more particularly, to a device with a bipolar transistor and a MOSFET transistor connected to one another in the “emitter switching” configuration.
BACKGROUND OF THE INVENTION
As is known, an “emitter switching” configuration is constituted by a vertical bipolar transistor, usually a high-voltage power transistor, and by an electronic switch in series with the emitter of the bipolar transistor. The electronic switch is advantageously a low-voltage power MOSFET transistor connected by its drain terminal to the emitter terminal of the bipolar transistor. By opening the electronic switch, it is possible to switch off the bipolar transistor extremely rapidly and this configuration is therefore used advantageously in applications in which the bipolar transistor is operated with rapid switching between its conductive and non-conductive states.
An integrated structure of a known device comprising a bipolar power transistor and a MOSFET transistor in the above-mentioned configuration, as shown in
FIG. 1
of the drawings appended to the present description, is formed on a substrate
10
of semiconductor material, for example, a monocrystalline silicon chip of the N+ type, that is, having a high concentration of N-type impurities. (It should be noted that, in the drawing, the concentrations of the N-type and P-type impurities are indicated, in conventional manner, by the addition of the − or + sign to the letters N and P; the letters N and P without the addition of a − or + sign denote concentrations of intermediate value).
Two epitaxial layers
11
and
12
of the N− and N types, respectively, are formed on the substrate
10
. The layer
11
, together with the substrate
10
, contains the collector region of the bipolar transistor. A metal layer
28
applied to the free surface of the substrate constitutes the collector electrode C.
A buried P− region, indicated
13
, formed between the epitaxial layers
11
and
12
, constitutes the base region of the bipolar transistor. A P+ insulation and deep base contact region
15
extends from the front surface of the chip, that is, from the surface remote from the collector electrode C, as far as the edge of the base region
13
, and an N insulation region, indicated
16
, is defined within the region
15
. A second, buried N-type region
14
with a high concentration of impurities, formed on the P− region
13
so as to form a pn junction therewith, constitutes the emitter region of the bipolar transistor.
A P region
25
which extends within the insulated region
16
constitutes the body region of the MOSFET transistor and contains the channel of that transistor. A region
26
formed within the body region
25
constitutes the source region of the MOSFET transistor. A strip
22
of electrically conductive material, disposed above the channel and insulated from the surface of the chip, constitutes the gate electrode of the MOSFET transistor, which is also an electrode of the device, indicated G.
Two electrically conductive surface contact strips
4
and
5
are formed on the source region
26
and on the insulation region
15
, respectively, in order to form the source electrode S of the MOSFET transistor and the base electrode B of the bipolar transistor, respectively. The drain region of the MOSFET transistor is constituted by the portion of the insulation N region
16
disposed between the buried emitter region
14
and the body region
25
and is not connected to external electrodes.
The structure described above usually constitutes an elemental functional component of a power device formed by a plurality of elemental components. The elemental components may be identical cells electrically connected in parallel with one another; in this case, the regions
13
and
14
are in the form of concentric circles or squares and each of the regions
15
is in the form of a circular or square frame. Alternatively, the elemental components may be elongate and may be disposed side by side to form a comblike or interdigitated structure. In this case, the buried base region is a single region common to all of the elemental components, the region
14
constitutes a “tooth” of a comb, and the insulation region
15
defines adjacent insulated regions
16
which also form “comb teeth”.
FIG. 2
shows an electrical circuit equivalent to the structure described above. This is a device formed by a bipolar transistor T
1
and by an N-channel MOSFET transistor T
2
, both with vertical conduction, in the emitter switching configuration. As can easily be seen, the emitter and base regions of the npn transistor T
1
are constituted by the regions
14
and
13
of
FIG. 1
, respectively, and the collector region of the transistor T
1
is constituted substantially by the regions of the epitaxial layer
11
and of the layer
10
which are disposed beneath the base region
13
. The source region of the MOSFET transistor T
2
is constituted by the N+ region
26
which is connected to the body region
25
on the surface by the metal strip
4
which constitutes the electrode S of the device. The drain region of T
2
is constituted by the zone of the epitaxial layer
12
disposed beneath the body region
25
bordering the emitter region
14
. The collector electrode of T
1
, the source electrode of T
2
, the base electrode of T
1
and the gate electrode of T
2
constitute the electrodes C, S, B and G of the device.
The resistance (RCSon) between the power terminals of the device during conduction is given by the sum of the resistance between the collector and the emitter of the bipolar power transistor T
1
and the resistance between the drain and source of the MOSFET transistor T
2
. Naturally, if the device is constituted by a plurality of elemental functional components, the resistance between its power terminals is given by the resistances RCSon of its components in parallel. In some applications the contribution of the vertical MOSFET transistor to the resistance RCSon is considered excessive.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a device with integrated bipolar and MOSFET transistors in an emitter switching configuration which, when conductive, has a lower resistance than known devices.
An embodiment of the invention is directed to device with a bipolar transistor and a MOSFET transistor connected to one another and integrated in a chip of semiconductor material. The device includes a semiconductive layer of a first conductivity type, which comprises a first conduction region of the bipolar transistor; a first buried region of a second conductivity type, which is buried in the semiconductive layer and forms a base region of the bipolar transistor; a second buried region of the first conductivity type, which is buried in the semiconductive layer, is positioned on the base region, and comprises a second conduction region of the bipolar transistor. In contrast to the prior art, the device also includes a well region of the second conductivity type, which extends downward from a front surface of the chip; a first MOSFET conduction region of the first conductivity type extending downward into the well region from the front surface of the chip; a second MOSFET conduction region of the first conductivity type, which contacts and extends upward from the second conduction region of the bipolar transistor into a position between and spaced apart from the first and second portions of the first MOSFET conduction region, thereby defining a channel of the MOSFET transistor within the well region and between the first and second MOSFET conduction regions; and a strip of electrically conductive material disposed over the channel and insulated from the channel by a layer of insulating material, the strip functioning a gate electrode of the MOSFET transistor.


REFERENCES:
patent: 5525826 (1996-06-01), Palara
patent: 5602416 (1997-02-01), Zambrano
patent: 5998855 (1999-12-01), Patti
patent: 60693

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