Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-11-30
2009-02-03
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S597000, C438S738000, C438S711000
Reexamination Certificate
active
07485581
ABSTRACT:
A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
REFERENCES:
patent: 5510645 (1996-04-01), Fitch et al.
patent: 6232214 (2001-05-01), Lee et al.
patent: 6297125 (2001-10-01), Nag et al.
patent: 6605541 (2003-08-01), Yu
patent: 6780753 (2004-08-01), Latchford et al.
patent: 6781192 (2004-08-01), Farrar
patent: 6806177 (2004-10-01), Strane et al.
patent: 6846741 (2005-01-01), Cooney, III et al.
patent: 6858153 (2005-02-01), Bjorkman et al.
patent: 6911397 (2005-06-01), Jun et al.
patent: 7008878 (2006-03-01), Hsu et al.
patent: 2003/0219988 (2003-11-01), Shan et al.
patent: 2003/0232474 (2003-12-01), Lai et al.
patent: 2003/0232509 (2003-12-01), Chung et al.
patent: 2004/0002217 (2004-01-01), Mazur et al.
patent: 2004/0072430 (2004-04-01), Huang et al.
patent: 2004/0126705 (2004-07-01), Lu et al.
patent: 2005/0110145 (2005-05-01), Elers
patent: 2006/0121721 (2006-06-01), Lee et al.
patent: 2006/0160353 (2006-07-01), Gueneau de Mussy et al.
patent: 2007/0049017 (2007-03-01), Hsieh
patent: 2007/0122977 (2007-05-01), Kim et al.
patent: 2007/0123016 (2007-05-01), Sadjadi et al.
patent: 2007/0123017 (2007-05-01), Sadjadi et al.
patent: 2007/0123053 (2007-05-01), Kim et al.
U.S. Appl. No. 11/291,303, entitled “Self-Aligned Pitch Reduction”, by inventors: Kim et al., filed Nov. 30, 2005.
U.S. Appl. No. 11/291,672, entitled “Device with Self Aligned Gaps for Capacitance Reduction”, by inventors: Sadjadi et al., filed Nov. 30, 2005.
Office Action dated Dec. 17, 2007 for related U.S. Appl. No. 11/291,672.
Notice of Allowance dated Feb. 19, 2008 for related U.S. Appl. No. 11/558,238.
International Search Report dated Mar. 20, 2007 from corresponding International Application No. PCT/US2006/044719.
Written Opinion dated Mar. 20, 2007 from corresponding International Application No. PCT/US2006/044719.
International Search Report dated Mar. 27, 2007 from related International Application No. PCT/US2006/044521.
Written Opinion dated Mar. 27, 2007 from related International Application No. PCT/US2006/044521.
International Search Report dated Apr. 24, 2007 from related International Application No. PCT/US2006/044708.
Written Opinion dated Apr. 24, 2007 from related International Application No. PCT/US2006/044708.
Huang Zhi-Song
Reza Sadjadi S. M.
Beyer Law Group LLP
Lam Research Corporation
Lindsay, Jr. Walter L
LandOfFree
Device with gaps for capacitance reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device with gaps for capacitance reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device with gaps for capacitance reduction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4087640