Device for the configuration of options in an integrated circuit

Details Device for the configuration of options in an integrated circuit Device for the configuration of options in an integrated circuit

1999-04-28

2000-10-31

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365210, G11C 702

Patent

active

061412570

ABSTRACT:
An option configuration device in an integrated circuit including, for each option bit to be configured, a configuration stage that includes a first set of non-volatile memory cells parallel-connected between a first node and a ground connection, and a second set of non-volatile memory cells parallel-connected between a second node and a ground connection. The first and second nodes are each connected to an input of a read circuit including a differential amplifier.

REFERENCES:
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5917753 (1999-06-01), Dallabora et al.
Saroj Pathak, et al, "A 25-ns 16K CMOS PROM Using a Four-Transistor Cell and Differential Design Techniques", Oct. 1985, IEEE Journal of Solid State Circuits, vol. 20, No. 5, pp. 964-970.
French Search Report dated Jan. 13, 1999 with annex on French Application No. 98-05572.

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