Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-02-18
2002-04-09
Sheikh, Ayaz (Department: 2155)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S031000, C714S045000, C714S046000, C714S732000, C714S735000, C714S736000
Reexamination Certificate
active
06370658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital video (or versatile) disc (DVD) reproducing apparatus, and in particular, to a device for testing a digital signal processor in a DVD reproducing apparatus, capable of allowing a user to observe a data processing status thereof, step by step.
2. Description of the Related Art
Being developed at the beginning of the 1980s, a CD (Compact Disc) player has made a remarkable development in a recording/reproducing technique as well as in data storage capacity. For instance, a recently developed recordable optical device such as a CD-WO (Write Once) and a CD-MO (Magneto Once) shows that the optical device is no more a read-only device. However, the storage capacity was limited due to the limited disc size and the data recording standard. Incidentally, an optical disc for a mini disc player adopting a data compression technique and a data buffering technique has an increased storage capacity. Above all, a digital video disc (DVD), which is a most recently developed recording medium for a digital moving picture, is suitable for a promising multi-media recording apparatus which can record an MPEG2 (Moving Picture Experts Group 2) digital image of over 2 hours.
FIG. 1
shows a schematic block diagram of a general DVD reproducing apparatus. With reference to
FIG. 1
, a disc motor
16
rotates a disc
10
at a constant speed, and a head
12
irradiates a laser beam on the disc
10
to read data recorded on the surface thereof. A sled motor
14
actuates an optical pickup
13
on which the head
12
is mounted, so as to move the optical pickup
13
forward and backward with respect to the rotating disc
10
. A signal reproducing device
21
amplifies an RF (Radio Frequency) signal output from the optical pickup
13
, removes noises therefrom, and performs synchronous detection, so as to reproduce the signal recorded on the disc
10
. A servo controller
27
controls rotation of the disc motor
16
, and also controls focusing and tracking of the optical pickup
13
. A system controller
24
controls an overall operation of the DVD reproducing apparatus. A digital signal processor
23
demodulates a signal output from the signal reproducing device
21
on the basis of 16-8 demodulation, and includes a synchronous detector which has digital PLL (Phase Locked Loop), descrambling, error detection, and track buffer control functions.
Specifically, a 16-8 demodulator (not shown) in the digital signal processor
23
detects a synchronous signal from the received data and demodulates the data to store it into a memory (i.e., track buffer)
22
. An error detector (not shown) in the digital signal processor
23
reads the data stored in the track buffer
22
to correct an error thereof and stores again the results into the track buffer
22
. Further, the digital signal processor
23
detector detects ID (identification) data representative of the disc position from the data stored in the track buffer
22
and transfers the ID data to the system controller
24
, and descrambles the data to store it again into the track buffer
22
. The data stored in the track buffer
22
will be transferred to a digital video decoding part at the request for the data. A key input part
25
, a user interface, includes a plurality of keys for inputting data or commands. A display
26
displays various operational states of the DVD reproducing apparatus.
A video decoder
32
decodes compressed video data output from the digital signal processor
23
into digital video data. A sub-video decoder
33
decodes sub-video information into still video information in the form of the digital video data. A video blanking information (hereinafter referred to as VBI for short) decoder
34
and a highlight information (HLI) decoder
35
decode data of still video form in such a manner as to conform with a special use. An audio decoder
36
decodes audio data from the digital signal processor
23
. A video mixer
29
mixes outputs of the video decoder
32
, the sub-video decoder
33
, the VBI decoder
34
, and the HLI decoder
35
. A video output circuit
30
converts the digital video data output from the video mixer
29
into an analog video signal and provides it to a monitor (not shown). An audio output circuit
31
converts the digital audio data output from the audio decoder
36
into an analog audio signal and provides it to a speaker (not shown). Here, the video decoder
32
, the sub-video decoder
33
, the VBI decoder
34
, the HLI decoder
35
and the audio decoder
36
constitute a known video/audio decoder (or MPEG2 decoder)
40
. A demultiplexer
28
demultiplexes the data output from the digital signal processor
23
to separately provide the bit stream type information, the video data, audio data, and the sub-video data to the MPEG2 decoder
40
, under the control of the system controller
24
.
FIG. 2
illustrates a device for testing the digital signal processor
23
shown in
FIG. 1
according to the prior art. In the drawing, a computer
70
generates test data, and displays the test results on a screen thereof so that a user of the computer may monitor the test results. A digital signal processor
23
is identical to that shown in
FIG. 1. A
microcomputer
52
controls an overall operation of the digital signal processor
23
. An interface
61
interfaces between the computer
70
and the digital signal processor
23
so as to transfer the test data from the computer
70
to the digital signal processor
23
. An SRAM (Static Random Access Memory)
63
stores 8-16 modulated data by 16 sectors (i.e., 32 Kbytes). An SRAM controller
62
generates an address signal and a control signal for reading and transferring the 8-16 modulated data of 16 sectors to the digital signal processor
23
. A serial interface
53
transfers the data read from the SRAM
63
to the digital signal processor
23
in the form of serial data. A track buffer
54
, which is a DRAM (dynamic RAM), stores the data output from the digital signal processor
23
and the test results for the digital signal processor
23
. A measuring device
80
analyzes contents of the track buffer
54
.
In accordance with the construction of the conventional test device, to test the digital signal processor
23
, data having the same format as that of the data received from the disc
10
should be applied to the test device from the exterior. Thus, the test device should previously have the data value. The input data is 16-8 demodulated at the digital signal processor
23
and then, stored into the track buffer
54
. To check whether the input data value is correct or not, an external device is needed to read the contents of the track buffer
54
. Moreover, to check an operational status of an error correction circuit, it is needed to perform the error correction in a row direction to check the contents of the track buffer
54
, and then perform the error correction in a column direction to check again the contents of the track buffer
54
. Further, to examine the data to be transmitted to the MPEG2 decoder
40
, an examination of the data which is descrambled is needed. For such a test operation, the test device needs to include an interface means for transferring the 8-16 modulated data from the computer
70
to the digital signal processor
23
, and another interface means for examining the contents of the track buffer
54
connected to the digital signal processor
23
for every operational step of the digital signal processor
23
. The interface
61
corresponds to the former, and the measuring device
80
corresponds to the latter. Even including the computer
70
, the conventional test device should read the contents of the track buffer
54
by using the separate measuring device
80
, which is very inefficient and causes a difficulty in analyzing the contents of the track buffer
54
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a device for effectively testing a digital signal processor and allowing a user to easily obs
Jean Frantz B.
Samsung Electronics Co,. Ltd.
Sheikh Ayaz
Staas & Halsey , LLP
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