Device for interfacing logic signals from the LLL level to the T

Details Device for interfacing logic signals from the LLL level to the T Device for interfacing logic signals from the LLL level to the T

1995-09-25

1999-03-09

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 73, 326 74, 326 81, H03K 190185

Patent

active

058806008

ABSTRACT:
A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

REFERENCES:
patent: 4779015 (1988-10-01), Erdelyi
patent: 5115434 (1992-05-01), Aizaki
patent: 5311083 (1994-05-01), Wanlass
patent: 5332935 (1994-07-01), Shyu
patent: 5361006 (1994-11-01), Cooperman et al.
patent: 5453704 (1995-09-01), Kawashima
patent: 5455526 (1995-10-01), Runas
1992 Symposium on VLSI Circuits, Digest of Technical Papers, Jun. 4-6, 1992, Seattle, pp. 82-83, Y. Nakagome et al. "Sub-IV Swing Bus Architecture for Future Low-Power ULSIs".

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