Device for dualizing main processors in an asynchronous transfer

Details Device for dualizing main processors in an asynchronous transfer Device for dualizing main processors in an asynchronous transfer

1997-06-30

2000-01-04

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

370395, 710130, G06F 1314, G06F 1338, H04L 1202

Patent

active

060121084

ABSTRACT:
A device for dualizing main processors in an ATM switch and a method therefor. The device for dualizing main processors in an asynchronous transfer mode switch, including: dualization controllers, each of which is in an active mode and a standby mode and connected s with memories of each of corresponding modes by way of an MBS, each of the dualization controller is comprised of: a first-in first-out; a write buffer connected between the MBUS in the active mode and the first-in first-out; a write controller for storing data stored at the write buffer at the first-in first-out; a read buffer connected between the MBUS in the standby mode and the first-in first-out; a read controller for simultaneously storing data stored at the first-in first-out, at the read buffer, checking status of the MBUS in the standby mode, and outputting the data stored at the read buffer to the MBUS in the standby mode.

REFERENCES:
patent: 4935894 (1990-06-01), Ternes et al.
patent: 5072440 (1991-12-01), Isono et al.
patent: 5123099 (1992-06-01), Shibata et al.
patent: 5153578 (1992-10-01), Izawa et al.
patent: 5450547 (1995-09-01), Nguyen et al.

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