Device for controlling data output for high-speed memory...

Details Device for controlling data output for high-speed memory... Device for controlling data output for high-speed memory...

2007-01-16

2007-01-16

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100

Reexamination Certificate

active

11108314

ABSTRACT:
Disclosed are a DDR group (DDR I, DDR II, DDR III, . . . ) data output control device for controlling a time point of data output by using a DLL circuit and a method thereof. The data output control device includes a latch part for storing data read out from a memory cell array through a read operation, a control part for controlling an operation of the latch part, and an initialization signal generating part for generating an initialization signal for resetting an operation of the control part, wherein the initialization signal is synchronized with a clock signal generated from a DLL circuit in the memory device.

REFERENCES:
patent: 6972998 (2005-12-01), Gibson et al.
patent: 2003/0108139 (2003-06-01), Jung

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