Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-02-13
2003-07-08
Clark, Sheila V. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S780000, C257S692000, C438S614000
Reexamination Certificate
active
06590294
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a device for bump probing integrated circuit packages equipped with bumps and a method for fabricating the device. More particularly, the present invention relates to a device for bump probing an integrated circuit package and a method for fabricating the device.
BACKGROUND OF THE INVENTION
As semiconductor integrated circuits continue to be dramatically reduced in size, the trend in electronic manufacturing has been toward increasingly smaller geometries particularly in integrated circuit technology in which a very large number of discrete circuit elements are fabricated on a single substrate or “wafer”. After fabrication, the wafer is divided into a number of rectangular-shaped chips or “dice” where each die presents a rectangular or other regular arrangement of metallized contact pads through which input/output connections are made. Although each die is eventually packaged separately, for efficiency sake, testing of the circuit formed on each die is preferably performed while the dies are still joined together on the wafer. One typical procedure is to support the wafer on a flat stage or “chuck” and to move the wafer in X, Y and Z directions relative to the head of the probing assembly so that the contacts on the probing assembly move from die to die for consecutive engagement with each die. Respective signal, power and ground lines are run to the probing assembly from the test instrumentation thus enabling each circuit to be sequentially connected to the test instrumentation.
One conventional type of probing assembly used for testing integrated circuits provides contacts that are configured as needle-like tips. These tips are mounted about a central opening formed in a probe card so as to radially converge inwardly and downwardly through the opening. When the wafer is raised beyond that point where the pads on the wafer first come into contact with these tips, the tips flex upwardly so as to skate forwardly across their respective pads thereby removing oxide buildup on the pads.
The problem with this type of probing assembly is that the needle-like tips, due to their narrow geometry, exhibit high inductance so that signal distortion is large in high frequency measurements made through these tips. Also, these tips can act in the manner of a planing tool as they wipe across their respective pads, thereby leading to excessive pad damage. This problem is magnified to the extent that the probe tips bend out of shape during use or otherwise fail to terminate in a common plane which causes the more forward ones of the tips to bear down too heavily on their respective pads.
Thus, in the course of testing semiconductor devices and circuits it becomes necessary to contact and electrically probe the devices and circuits to ascertain their function and determine failure mechanisms. To accomplish this, a finely pointed probe tip or group of finely pointed probe tips is brought into contact with the device or circuit by using pads connected to the device or circuit. As semiconductor devices become smaller and circuits denser, it becomes difficult to make electrical contact with the device with conventional probes, as the probe tips are either too large or too blunt to selectively contact only the intended device or circuit because they have a propensity to contact adjacent structures. Or, the tips are so thin as to bend when contact is attempted and slide off the probe terminal target circuit being tested. When multiple probes are required, it is often not possible to bring the correct number of probe tips close enough to each other because the size of the bodies will physically interfere with one another or will block the view of the target area being tested, thereby making alignment difficult or impossible.
As a result of these problems, pads on semiconductor devices which can number several hundred are often limited by the probe assemblies or probe rings used because of the size of the probe tips. This is especially true in the street or kerf regions between active dies on semiconductor wafers, wherein special test and process monitoring devices and circuits are often fabricated. The actual devices and monitoring structures are often very much smaller than the pads connected to them. A more compact probe assembly would allow smaller pads to be used allowing more devices in the same space or the same number of devices in a smaller space.
The present inventors thus recognize based on the foregoing, that a need exists for an acceptable micro tip that can be utilized with micro probes as semiconductor circuits continue to shrink. Users typically waste a great deal of time and effort attempting to fabricate an acceptable micro tip. To date, a reliable method for fabricating an acceptable micro tip has not been evidenced. The present inventors believe that implementing a micro tip in accordance with the invention described herein can thus solve these problems.
It is therefore an object of the present invention to provide a device for bump probing that does not have the drawbacks and shortcomings of the conventional devices.
It is another object of the present invention to provide a device for bump probing that can be fabricated by a micro-electro-mechanical system (MEMS) technique.
It is a further object of the present invention to provide a device for bump probing wherein the device can be controlled by an electrostatic force.
It is another further object of the present invention to provide a device for bump probing wherein the device can be controlled by a direct current flown to electrodes in the device.
It is still another object of the present invention to provide a method for fabricating a device for bump probing which can be carried out on a semiconducting substrate.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for fabricating a device for bump probing and the device fabricated are provided.
In a preferred embodiment, a method for fabricating a device for bump probing can be carried out by the operating steps of providing a semiconducting substrate; forming a first insulating material layer on the semiconducting substrate; depositing a first metal layer with a first metal and forming spaced-apart a first and a second electrode; depositing a second insulating material layer on top of the semiconducting substrate embedding the first and second electrodes; forming a via hole through the insulating material layer exposing a tip portion of the second electrode; depositing a second metal layer on top of the second insulating material layer and filling the via hole with a second metal forming an electrode support; depositing a third metal layer on top of the second metal layer; patterning the third metal layer into at least four finger tips; patterning the second metal layer into at least four fingers for supporting the at least four finger tips, the at least four fingers are in electrical communication with the electrode support and overhang the first electrode; and etching away the second insulating material layer to release the at least four fingers such that the at least four finger tips curve upwardly.
The method for fabricating a device for bump probing may further including the step of flowing a direct current of positive polarity to the first electrode and a direct current of negative polarity to the second electrode, or the step of flowing a direct current to the first and second electrodes such that an electrostatic force is generated to pull the at least four finger tips downwardly to a horizontal plane. The method may further include the step of depositing the first and the second insulating material layers from a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride. The method may further include the step of depositing the first metal layer with a first metal selected from the group consisting of Cu, Al and CuAl alloys, or the step of depositing the second metal layer with a second metal selected from the group consisting of Cu, Au a
Lee Cheng-Hong
Lee Hsin-Li
Clark Sheila V.
Industrial Technology Research Institute
tung & Associates
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