Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-29
2001-10-09
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06300200
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices and more particularly to a method of fabricating a non-volatile memory device used in a non-overlapping implant.
BACKGROUND OF THE INVENTION
FIG. 1
shows a schematic plan view of a conventional MOSFET-based ROM device
10
which is specially designed for permanent storage data. This ROM device includes a plurality of memory cells as exemplarily indicated by the dash boxes labeled with the reference numerals
12
,
14
, which can be accessed via an array of intercrossed world lines WL
1
, WL
2
, WL
3
and an array of buried bit lines BL
1
, BL
2
, BL
3
. World lines passe over the tops of the buried bit lines. Each of the memory cells is associated with one segment of the word line between each neighboring pair of the bit lines under which one channel region is formed labeled with the reference numeral
16
. Whether the memory cell
12
stores the data
0
or
1
is dependent on whether its associated channel region
16
is doped with impurity or not.
FIG. 2
shows a cross section of the device
10
taken along line
1
B—
1
B in FIG.
1
. Device
10
includes a P-doped silicon substrate
20
with buried N+ bit lines
26
. Over the substrate is formed a gate oxide layer
22
upon which is formed a polysilcon world lines
24
. Photoresist mask with a pattern
25
is formed over the polysilicon word line
24
for the process of code ion implantation. The section in
FIG. 2
shows code implantation of implanted boron ion region
28
.
To achieve microminiaturization of integrated circuit devices, individual elements have been made very small and the elements have been closely packed. As read only memory devices scaled down in dimensions, there is a continuous challenge to maintain close spacing between the buried bit lines to obtain density cell structures. Also, the spacing between the bit lines and code implant areas is critical to maintaining consistent bit line resistance that is a important factor to ROM read speed. Code implants and bit lines are composed of an opposite type impurities such that N+ bit lines and P+ code implants or P+ bit lines and N+ code implants. A large bit line resistance due to a code impurity overlap will degrade the data reading speed.
As shown in
FIG. 2
, conventional photolithography processes are used to form photoresist pattern
25
on the surface, leaving opening area where the code implants are desired. The remaining photoresist pattern
25
is used as a code implant mask. When the bit lines are N+ type regions, a boron ion is normally used for the code implant. The surface is implanted with boron forming code implant region
28
.
Referring to
FIG. 3
, a ROM code implant region is located below an opening area in the photoresist mask
25
at the intersection of the word line and the space between two adjacent bit lines. The section in
FIG. 3
shows a code implantation
30
of implanted boron ions
29
. The code implantation
30
overlap the buried bit lines
26
due to the mask shift indicated by dash line thereby increasing the bit line resistance due to the opposite type impurity. On the other hand, the most advanced ULSI has a minimum feature size of 0.15 um, which is very close to the resolution limit of optical photolithography because of the light source. The code implantation area is about 0.15 um
2
in a 0.15 um process. The light refraction is often introduced to the resolution difference, which may cause the overlap. The photo masks manufacturing therefore need optic proximity correction process. Hence, in a conventional photolithography process, overlay control is very time-consuming to carry out. In addition, to reduce manufacturing cost, the process of masks manufacturing must be relatively simple.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabrication a ROM semiconductor device to overcome the drawback of conventional fabrication method, which adds the step of forming a protective layer before forming photoresist pattern, allowing the overlay control to be simplified.
Another objective of the invention is to provide a process to eliminate the using of a special mask needing optic proximity correction process.
In accordance with the above objectives of the present invention, a new method is provided for fabricating a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, the buried bit lines being oriented in a first direction, a gate oxide layer above the substrate and word lines formed above the gate oxide layer, which comprises theses following steps. A dielectric layer is formed over the word lines and gate oxide layer. A first photoresist layer is formed over the dielectric layer. The first photoresist layer is then selectively exposed to develop first opening area over the photoresist layer, wherein the opening area centered between the adjacent bit lines. The dielectric layer is etched through the first opening area, the first photoresist layer is stripped. A second photoresist layer is formed over the dielectric layer and then selectively exposes the second photoresist layer to develop second opening area over the second photoresist layer to define a pattern of code ion implantation. A code implant dopant implants through the second opening area down into the substrate second opening area, and stripped the second photoresist layer.
REFERENCES:
patent: 5523251 (1996-06-01), Hong
patent: 5585297 (1996-12-01), Sheng et al.
Macronix International Co. Ltd.
Tsai Jey
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