Device directed memory barriers

Details Device directed memory barriers Device directed memory barriers

2011-07-19

2011-07-19

Lee, Chun-Kuan (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S028000, C710S110000, C711S154000

Reexamination Certificate

active

07984202

ABSTRACT:
Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.

REFERENCES:
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patent: 7500045 (2009-03-01), Hofmann et al.
patent: 2007/0214298 (2007-09-01), Sullivan et al.
patent: 9938085 (1999-07-01), None
patent: 2006102636 (2006-09-01), None
International Search Report-PCT/US2008/065451, International Search Authority—European Patent Office—Sep. 26, 2008.
Written Opinion—PCT/US2008/065451, International Search Authority—European Patent Office—Sep. 26, 2008.

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