Device architecture and process for improved vertical memory...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S203000, C257S207000, C257S211000, C257S301000, C257S302000, C257S328000, C257S908000

Reexamination Certificate

active

06930324

ABSTRACT:
An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines. The test structure provides a convenient means to carry out reliability investigations on the gate oxide of the vertical FET transistors and on the capacitor dielectric in the deep trenches, capacitance measurements between the word lines, and between the word lines and other circuit layers, as well as capacitance measurements between the bit lines and between the bit lines and other circuit layers, and thus facilitates diagnosis of possible fault sources arising during the production process.

REFERENCES:
patent: 5844915 (1998-12-01), Saitoh et al.
patent: 6388927 (2002-05-01), Churchill et al.
patent: 6617180 (2003-09-01), Wang
patent: 2003/0003611 (2003-01-01), Weiner et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Device architecture and process for improved vertical memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device architecture and process for improved vertical memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device architecture and process for improved vertical memory... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3458095

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.