Device arbitration including peer-to-peer access arbitration

Details Device arbitration including peer-to-peer access arbitration Device arbitration including peer-to-peer access arbitration

1999-08-19

2002-11-12

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S242000, C710S243000, C710S305000

Reexamination Certificate

active

06480917

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to an improved information transfer system in a computer related environment.
BACKGROUND OF THE INVENTION
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term “bandwidth” is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in “holding” buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or “PCI” system bridge circuit buffers are assigned to PCI devices, which are installed in PCI “slots” and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted into PCI “slots”, i.e. into board connector terminals mounted on a system motherboard.
Standard PCI-PCI bridges are utilized in the industry today as a means to provide added slots for PCI devices since individual PCI busses are limited to 10 loads per bus at 33 MHz and 5 loads at 66 MHz (a soldered device counts as one load and a slotted device counts as two loads). This requires a combination of multiple PCI host bridges and/or multiple standard PCI-PCI bridges per each server drawer where server drawers typically house 14-16 PCI slots per drawer. The total integrated circuit (IC) or chip and packaging cost is expensive utilizing standard components.
Thus, there is an increasing need for an improved computer system which is designed to be able to efficiently handle greater numbers of peripheral adapters in computer systems.
SUMMARY OF THE INVENTION
A method and implementing system is provided in which multiple PCI busses are managed through a combination multiple node PCI-to-PCI bridge including a non-blocking PCI Router (PCIR) circuit. The bridge circuit includes an internal arbiter for the primary PCI bus interface of the bridge to determine which of the multiple secondary nodes gains access to the bridge primary bus at a given time. When multiple nodes have pending transactions destined for the primary PCI bus, a bridge internal methodology is provided to avoid deadlocks and provide fair access to the primary bus by each of the secondary PCI nodes. In the case of a single attached PCI device at each of the secondary PCI nodes, an internal arbiter is provided for each PCI secondary node. In an exemplary embodiment, an internal REQ#/GNT# pair is provided to each secondary node, for each source node to arbitrate for a respective target node. An external REQ#/GNT# pair is provided on each secondary PCI bus for the attached device at the node to also arbitrate for that respective PCI bus. The exemplary internal fairness arbitration methodology is implemented for each arbiter at each PCI secondary bus. The exemplary arbitration methodology uses a round-robin approach to determine which internal request from another node will be next to request access for a specific secondary PCI bus. Further, the preferred methodology gives priority to the externally attached device when it is requesting the bus.


REFERENCES:
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patent: 5771359 (1998-06-01), Galloway et al.
patent: 5838899 (1998-11-01), Leavitt et al.
patent: 5909594 (1999-06-01), Ross et al.
patent: 6175888 (2001-01-01), Guthrie et al.
patent: 6330656 (2001-12-01), Bealkowski et al.

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