Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-06-07
2002-05-28
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S265000, C714S792000
Reexamination Certificate
active
06397367
ABSTRACT:
PRIORITY
This application claims priority to an application entitled “Channel Coding Device and Method” filed in the Korean Industrial Property Office on Jun. 5, 1998 and assigned Ser. No. 98-20990, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a channel coding device and method for a communication system. Specifically, the present invention relates to a rate matching device and methods for inserting known bits in an input source data bit stream, channel coding the bit-inserted data stream and then, puncturing the channel coded data symbols.
2. Description of the Related Art
In a communication system, a rate of source user data is changed to a rate of channel symbols during data transmission via a channel. Particularly, in a spread spectrum communication system, since a chip rate for spreading is fixed, a channel symbol rate should be changed in order to be a multiple of the chip rate after multiplexing various service channels. Such a procedure is called rate matching.
With reference to
FIG. 1
, there is illustrated a block diagram of a conventional rate matching scheme for a source data rate of 64 Kbps. A CRC (Cyclic Redundancy Code) generator
101
adds 13 CRC bits to source coded user data input. A rate ⅓ (R=⅓) channel coder
102
codes the CRC-added data into 653×3=1959 symbols. Herein, a description will be made regarding a method of changing the number of data symbols to be transmitted from 1959 symbols to 2048 symbols. To this end, a rate matcher
103
repeats 89 symbols. However, a simple symbol repetition may cause degradation in performance of the system according to a channel condition as discussed in CSELT, “Power Control Parameters Optimization in W-CDMA Down-Link”, SMG2 Layer
1
Expert Group Agenda Item 7, Oslo, Apr. 1-2, 1998 (the CSELT Reference).
The channel coder
102
of
FIG. 1
includes a convolutional coder, a Reed-Solomon coder, a concatenated coder in which the convolutional coder is coupled to the Reed-Solomon coder, and a turbo coder in which plural convolutional coders are coupled in series or parallel. Herein, a detailed description of the respective coders will be avoided for convenience. Instead, a description will be made as to the turbo coder. The turbo coder, a parallel concatenated coder, codes N-bit frame data into parity symbols using two simple parallel concatenated codes, wherein recursive systematic convolutional (RSC) codes are generally used for the constituent codes.
FIGS. 2 and 4
are block diagrams illustrating a conventional turbo coder and a turbo decoder, respectively. Reference can be made to U.S. Pat. No. 5,446,747 issued on Aug. 29, 1995 to Berrou for a comprehensive description. The turbo coder of
FIG. 2
includes a first constituent coder
201
, a second constituent coder
202
, and an interleaver
211
interconnected between the constituent coders
201
and
202
. For the first and second coders
201
and
202
, an RSC coder is typically used, which is well-known in the art. The interleaver
211
has the same size as a frame length, N, of input data bit stream d
k
, and changes arrangement of the input data bit stream d
k
to be provided to the second constituent coder
202
to decrease the correlation among the data bits. Therefore, an output parallel concatenated code for the input data bit stream d
k
becomes x
k
(i.e., d
k
without modification) and y
1k
, and y
2k
,
A turbo decoder for decoding the output of the turbo coder of
FIG. 2
is disclosed in U.S. Pat. No. 5,446,747, and schematically illustrated in FIG.
4
. Since the turbo decoder iteratively decodes received data in a frame unit using a MAP (Maximum A Posterior Probability) decoding algorithm, an increase in frequency of iterative decoding will decrease a bit error rate (BER). For the turbo decoder, a MAP decoder or a SOVA (Soft-Out Viterbi Algorithm) decoder is typically used, which can provide soft-decision iterative decoding.
FIG. 3
illustrates a convolutional coder with a constraint length 9 (K=2) and a coding rate ⅓ (R=⅓). For decoding an output of the convolutional coder, a Viterbi decoder is generally used which employs a Viterbi algorithm. A detailed description of the Viterbi decoder is avoided herein.
FIG. 5
is a block diagram illustrating a transmission part of a known communication system, which multiplexes user data and control data and transmits the multiplexed data. The user data is coded by a first source coder
501
and a first channel coder
502
. Further, the control data is coded by a second source coder
511
and a second channel coder
512
and then multiplexed with the coded user data by a multiplexer
503
. The multiplexed user data and control data is rate matched at a rate matcher
504
by symbol repetition, puncturing or puncturing-after-symbol repetition. The rate matched symbols are provided to a transmitter
507
via a channel interleaver
505
and a modulator
506
.
FIG. 6
is a block diagram illustrating a transmission part of another known communication system which multiplexes first and second user data and control data and transmits the multiplexed data. The first and second user data are channel coded by first and second channel coders
602
and
612
, respectively, and then, rate matched by first and second rate matchers
603
and
613
according to their service option and class by symbol repetition, puncturing or puncturing-after-symbol repetition. Similarly, the control data is channel coded by a third channel coder
622
and then, rate matched by a third rate matcher
623
. Outputs of the first to third rate matchers
603
,
613
and
623
are multiplexed by a multiplexer
604
and then, finally rate matched by a channel rate matcher
605
. The channel rate matched symbols are provided to a transmitter
608
via a channel interleaver
606
and a modulator
607
.
A description will now be made as to symbol repetition performed for matching rates of symbols outputted from the channel coders
602
,
612
and
622
. A simple repetition of the channel coded symbols is a very simple symbol repetition method. However, the simple symbol repetition is not suitable for error correction. This is because in the light of the channel coded symbols, although a BER for the case where all the symbols are repeated two times (i.e., a rate ½) is similar to a BER for the case where the symbols are not repeated (i.e., a rate 1), a performance degradation may occur according to a channel condition in the case where the respective symbols are unequally repeated (see the CSELT Reference). Therefore, when unequal symbol repetition is performed for rate matching, efficiency of the overall system typically decreases.
Further, reference will be made to a turbo coder of
FIG. 2
having a constraint length 3 (K=3). Outputs of the turbo coder include non-coded data bit x
k
and channel coded data parity bits y
1k
and y
2k
. When the data bit x
k
is punctured for rate matching or various symbol rates, performance degradation is significant. In addition, when the parity bits y
1k
and y
2k
are simultaneously punctured at a time k, there exist no parity bits for a data bit at the time k. In the K=3 turbo coder, when the same parity bits y
1k
and y
1k+1
or the same parity bits y
2k
and y
2k+1
are simultaneously punctured, there exist no parity bits for data bits at the time k and k+1, so that a performance degradation occurs even though iterative decoding is performed. That is, when the parity bits outputted from the first and second constituent coders are consecutively punctured as many as the number of memories in the turbo coder, performance degradation occurs.
Therefore, for rate matching which requires symbol repetition, it is possible to guard against performance degradation by providing a channel coder which inserts specific bits in an input data bit stream and encodes the bit-inserted data bit stream. It is assumed herein tha
Lee Hyeon-Woo
Park Chang-Soo
Baker Stephen M.
Samsung Electronics Co,. Ltd.
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