Device and method for stress testing a semiconductor memory

Details Device and method for stress testing a semiconductor memory Device and method for stress testing a semiconductor memory

1998-02-19

1999-09-28

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

365190, G11C 700

Patent

active

059599138

ABSTRACT:
A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.

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