Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-08-20
2002-04-16
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S788000, C375S265000, C375S340000
Reexamination Certificate
active
06374386
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a channel encoding device and method for a communication system, and in particular, to a device and a method for inserting previously known bits in an input stage of a channel encoding device.
2. Description of the Related Art
In communication systems for processing voice, character, image and video signals, data is generally transmitted on a frame unit basis. A frame is defined as a basic timing interval in the system. Further, in a system for communicating such frame data, a channel encoder for error correction should also encode data on the frame unit basis. In this case, the channel encoder performs zero tail biting to indicate the termination of each frame so that a decoder can efficiently decode the frames using that information. Encoder tail bits represent a fixed sequence of bits added to the end of a data frame to reset the convolutional encoder to a known state. An IS-95 system typically uses a non-recursive systemic convolutional encoder, which adds a sequence of zero (0) bits to the end of each frame equal to the number of delays, to implement frame termination. However, in contrast to the non-recursive systemic convolutional encoder, a recursive systemic encoder cannot add the zero bits to the end of the frame to implement the frame termination, because input bits are fed back to the delays.
FIG. 1
illustrates a block diagram of a conventional parallel turbo encoder, which is disclosed in U.S. Pat. No. 5,446,747 issued to Berrou. The encoder of
FIG. 1
is one type of conventional recursive systemic encoder. The turbo encoder encodes an N-bit input frame into parity symbols using two simple constituent encoders, and can be configured to have either a parallel or serial structure. In addition, the turbo encoder of
FIG. 1
uses recursive systemic convolutional codes as constituent codes.
The turbo encoder of
FIG. 1
includes an interleaver
120
interposed between a first constituent encoder
110
and a second constituent encoder
130
. The interleaver
120
has the same size as a frame length, N, of input data bits and re-arranges the order of the data bits input to the second constituent encoder
130
to reduce the correlation between the outputs of the first and second encoders.
The first constituent encoder
110
encodes the input data bits and the interleaver
120
interleaves (or randomizes) the bits in the input data stream according to a specified rule so that burst errors introduced by the channel can be converted to random errors. The second constituent encoder
130
encodes the output of the interleaver
120
.
FIG. 2
is a diagram illustrating a termination scheme in the recursive systemic convolutional encoder of FIG.
1
. For more detailed information, see D. Divsalar and F. Pollara, On the Design of Turbo Dodes, TDA Progress Report 42-123, Nov. 15, 1995. Here, frame data input to the first and second constituent encoders
110
and
130
is assumed to be 20-bit data. In
FIG. 2
, D
1
-D
4
denotes delays and XOR
1
-XOR
6
exclusive OR gates.
Referring to
FIG. 2
, the operative steps to perform encoding are as follows. A switch SW
1
is maintained in the ON position and a switch SW
2
is maintained in the OFF position. Then, the 20-bit input frame data is applied in sequence to the delays D
1
-D
4
and exclusively ORed by the exclusive OR gates XOR
1
-XOR
6
, thus outputting encoded bits at the output of exclusive OR gate XOR
6
. When the 20 data bits are all encoded in this manner, the switch SW
1
is switched OFF and the switch SW
2
is switched ON, for frame termination. Then, the XOR gates XOR
1
-XOR
4
exclusively OR the output data bits of the delays and the corresponding fed-back data bits, respectively, thereby outputting zero bits. The resulting zero bits are again input to the delays D
1
-D
4
and stored therein. These zero bits input to the delays D
1
-D
4
become tail bits, which are applied to a multiplexer.
The multiplexer multiplexes the encoded data bits and the tail bits output from the constituent encoder. The number of generated tail bits depends on the number of delays included in the constituent encoders
110
and
130
. The termination scheme of
FIG. 2
generates 4 tail bits per frame plus additional encoded bits generated for each of the respective tail bits, undesirably increasing the overall final encoded bit count, which leads to a decrease in the bit rate. That is, when the bit rate is defined as;
Bit Rate=(the Number of Input Data Bits)/(the Number of Output Data Bits),
a constituent encoder having the structure of
FIG. 2
has a bit rate of
Bit Rate=(the Number of Input Data Bits)/{(the Number of Encoded Data Bits)+(the Number of Tail Bits)+(the Number of Encoded Bits for the Tail Bits)}.
Accordingly, in
FIG. 2
, since the frame data is composed of 20 bits and the number of delays equals 4, the bit rate becomes 20/28.
It is therefore apparent that the recursive systemic convolutional encoders performance depends upon the tailing method, because it is difficult to perfectly tail the turbo codes.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a device and method for inserting bits in each channel frame at positions having a higher error occur range probability having a specific value at a last position of frame data bits, wherein the last position has a high error occurrence probability during decoding in a turbo coding device.
It is another object of the present invention to provide a device and method for inserting specific bits at the tail positions of data bit streams being respectively input to a first constituent encoder and a second constituent encoder in turbo coding device.
It is a further object of the present invention to provide a device and method for inserting specific bits at the tail positions of data bit streams being respectively input to a first constituent encoder and a second constituent encoder in a turbo coding device, wherein a position of the specific bit inserted in the second constituent encoder is shifted forward when the positions of the specific bits inserted in the first and second constituent encoders overlap each other.
To achieve the above objects, a turbo coding device according to the present invention includes a bit inserter for inserting one or more specific bits at tail positions of a data bit stream being input to a first constituent encoder, and inserting at least one specific bit at a last position of an interleaved data bit stream being input to a second constituent encoder; the first constituent encoder for encoding the specific bit-inserted data bits to generate first parity symbols; an interleaver for interleaving the specific bit-inserted data bits; the second constituent encoder for encoding the interleaved data bits to generate second parity symbols; and a multiplexer for multiplexing outputs of the bit inserter, the first constituent encoder and the second constituent encoder.
REFERENCES:
patent: 5446747 (1995-08-01), Berrou
patent: 6044116 (2000-03-01), Wang
patent: 6088387 (2000-07-01), Gelblum et al.
patent: 6212654 (2001-03-01), Lou et al.
Kim Jae-Yeol
Park Chang Soo
Dilworth & Barrese LLP
Moise Emmanuel L.
Samsung Electronics Co,. Ltd.
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