Device and method for generating and distributing coded...

Multiplex communications – Communication over free space – Combining or distributing information via code word channels...

Reexamination Certificate

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C370S320000, C370S441000

Reexamination Certificate

active

06400703

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a CDMA communication system, and in particular, to a device and method for generating and distributing coded symbols capable of preventing degradation in channel performance during data transmission.
2. Description of the Related Art
Code Division Multiple Access (CDMA) communication systems are implemented according to the IS-95 standard. With an increase in the sophistication of CDMA communication technology and a decrease in usage costs, there has been an exponential growth in the number of subscribers of CDMA communication services. Accordingly, many methods have been proposed for meeting subscribers' ever-increasing demands for high quality CDMA service. For example, several methods for improving a forward link structure in the CDMA communication system have been proposed.
One such method for improving the forward link structure, especially a forward link fundamental channel designed for a third generation multicarrier CDMA system, was proposed in the TIA/EIA TR45.5 conference and approved on May 15, 1998 by the Telecommunications Industry Association (TIA). A forward link structure for a multicarrier CDMA communication system is illustrated in FIG.
1
.
With reference to
FIG. 1
, a channel encoder
10
encodes input data, and a rate matcher
20
repeats and punctures symbols outputted from the channel encoder
10
. Here, the data input to the channel encoder
10
has a variable bit rate. The rate matcher
20
repeats and punctures the coded data bits (i.e., symbols) outputted from the channel encoder
10
to match symbol rates for the data having the variable bit rate. A channel interleaver
30
interleaves an output of the rate matcher
20
. A block interleaver is typically used for the interleaver
30
.
A long code generator
91
generates a long code which is identical to that used by the subscriber. The long code is a unique identification code for the subscriber. Thus, different long codes are assigned to the respective subscribers. A decimator
92
decimates the long code to match a rate of the long code to a rate of the symbols outputted from the interleaver
30
. An adder
93
adds an output of the channel interleaver
30
and an output of the decimator
92
. An exclusive OR gate is typically used for the adder
93
.
A demultiplexer
40
sequentially multiplexes data outputted from the adder
93
to multiple carriers A, B and C. First to third binary-to-four level converters
51
-
53
convert signal levels of binary data outputted from the demultiplexer
40
by converting input data of “0” to “+1” and input data of “1” to “−1”. First to third orthogonal modulators
61
-
63
encode data outputted from the first to third level converts
51
-
53
with corresponding Walsh codes, respectively. Here, the Walsh codes have a length of 256 bits. First to third spreaders
71
-
73
spread outputs of the first to third orthogonal modulators
61
-
63
, respectively. Here, QPSK (Quadrature Phase Shift Keying) spreaders can be used for the spreaders
71
-
73
. First to third attenuators (or gain controllers)
81
-
83
control gains of the spread signals outputted from the first to third spreaders
71
-
73
according to corresponding attenuation signals GA-GC, respectively. Here, the signals outputted from the first to third attenuators
81
-
83
become different carriers A, B and C.
In the forward link structure of
FIG. 1
, the channel encoder
10
, having a coding rate of R=1/3, encodes the input data into 3 coded data bits (i.e., code words or symbols) per bit. Such coded data bits are demultiplexed to the three carriers A, B and C after rate matching and channel interleaving. The multicarrier CDMA communication system of
FIG. 1
can be modified to a single carrier CDMA communication system by removing the demultiplexer
40
and using only one level converter, one orthogonal modulator, one spreader and one attenuator.
FIG. 2
is a detailed diagram illustrating the channel encoder
10
, the rate matcher
20
and the channel interleaver
30
. In
FIG. 2
, data of a first rate is composed of 172 bits (fall rate) per 20 ms frame; data of a second rate is composed of 80 bits (½ rate) per 20 ms frame; data of a third rate is composed of 40 bits (¼ rate) per 20 ms frame; and data of a fourth rate is composed of 16 bits (⅛ rate) per 20 ms frame.
First to fourth CRC generators
111
-
114
generate CRC bits corresponding to the respective input data having different rates and add the generated CRC bits to the input data. Specifically, 12-bit CRC is added to the 172-bit data of the first rate; 8-bit CRC is added to the 80-bit data of the second rate; 6-bit CRC is added to the 40-bit data of the third rate; and 6-bit CRC is added to the 16-bit data of the fourth rate. First to fourth tail bit generators
121
-
124
add 8 tail bits to the CRC-added data, respectively. Therefore, the first tail bit generator
121
outputs 192 bits; the second tail bit generator
122
outputs 96 bits; the third tail bit generator
123
outputs 54 bits; and the fourth tail bit generator
124
outputs 30 bits.
First to fourth encoders
11
-
14
encode data output from the first to fourth tail bit generators
121
-
124
, respectively. A convolutional encoder having a constraint length of K=9 and a coding rate of R=1/3 can be used for the encoders
11
-
14
. In this case, the first encoder
11
encodes the 192-bit data output from the first tail bit generator
121
into 576 symbols of full rate; the second encoder
12
encodes the 96-bit data output from the second tail bit generator
122
into 288 symbols of ½ rate; the third encoder
13
encodes the 54-bit data output from the third tail bit generator
123
into 162 symbols of about ¼ rate; and the fourth encoder
14
encodes the 30-bit data output from the fourth tail bit generator
124
into 90 symbols of about ⅛ rate.
The rate matcher
20
includes repeaters
22
-
24
and symbol deletion devices
27
-
28
. The repeaters
22
-
24
repeat symbols outputted from the second to fourth encoders
12
-
14
according to predetermined times to increase output symbol rates thereof to the fall rate. The symbol deletion devices
27
and
28
delete symbols outputted from the repeaters
23
and
24
which exceed the symbols of the full rate in number. Since the second encoder
12
outputs 288 symbols which is ½ the 576 symbols outputted from the first encoder
11
, the second repeater
22
repeats the received 288 symbols two times to output 576 symbols. Further, since the third encoder
13
outputs 162 symbols which is about ¼ the 576 symbols outputted from the first encoder
11
, the third repeater
23
repeats the received 162 symbols four times to output 648 symbols which exceeds the 576 symbols of full rate in number. To match the symbol rate to the full rate, the symbol deletion device
27
deletes every ninth symbol to output 576 symbols of full rate. In addition, since the fourth encoder
14
outputs 90 symbols which is about ⅛ the 576 symbols output from the first encoder
11
, the fourth repeater
24
repeats the received 90 symbols eight times to output 720 symbols which exceeds the 576 symbols of full rate in number. To match the symbol rate to the full rate, the symbol deletion device
28
deletes every fifth symbol to output 576 symbols of full rate.
First to fourth channel interleavers
31
-
34
interleave the symbols of full rate outputted from the first encoder
11
, the second repeater
22
, the symbol deletion device
27
and the symbol deletion device
28
, respectively. Forward Error Correction (FEC) is used to maintain a sufficiently low Bit Error Rate (BER) of a mobile station for a channel having a low signal-to-noise ratio (SNR) by providing a channel coding gain. The forward link for the multicarrier communication system can share the same frequency band with the forward link for the IS-95 system in an overlay method. However, the overlay method

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