Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-03
2003-01-07
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S227000, C438S228000, C438S280000, C257S368000, C257S369000
Reexamination Certificate
active
06503787
ABSTRACT:
The present invention is directed, in general, to a device and method for forming a semiconductor device local interconnect and, more specifically, to a method of forming an interconnect within a semiconductor tub.
BACKGROUND OF THE INVENTION
Much attention is given to certain aspects of integrated circuit (IC) technology, such as the number or dimensions of the devices in the circuit and circuit processing speeds that can reach millions of instructions per second (MIPS). Clearly, progress in these areas has great appeal and is readily understood. However, there are other aspects of very large scale integrated (VLSI) circuit technology that are of significant importance. For example, the various devices, e.g., sources, gates and drains, of the integrated circuits must be electrically connected to be of any use within a larger electrical circuit. In the prior art, active devices have been successfully connected by depositing patterned metal, usually aluminum but more recently copper, in one or more layers above the device layers. To interconnect the appropriate devices and metal layers, metal plugs, typically tungsten (W) are formed through the dielectric layers and between the different metal layers. Significantly, the metal layering process is much more expensive than other processes such as ion implantation. The methods for defining and forming such patterned metal layers, tungsten plugs, and dielectric layers are well known to those who are skilled in the art.
Market demands for faster and more powerful integrated circuits have resulted in significant growth in the number of devices per cm
2
, i.e., a higher packing fraction of active devices. This increased packing fraction invariably means that the interconnections for ever-more-complicated circuits are made to smaller dimensions than before. However, as device sizes reach 0.25 &mgr;m and below, physical limitations of the metal deposition processes prevent reducing the scale of the device interconnections at the same rate as the devices.
Accordingly, what is needed in the art is a method for forming semiconductor device interconnections that is more cost effective and is not size limited as in the prior art. The present invention addresses this need.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer with the first and second active areas in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.
Thus, the present invention provides an interconnect that uses the tub region for device electrical connections. Because of the unique location of the interconnect, device space above the tub region is better utilized to allow for a higher packing fraction.
In one embodiment, the interconnect comprises an implanted pattern formed in the tub and that extends into the first and second active areas. The first and second active areas may be source or drain regions and in some embodiments may include gates.
In another aspect of the present invention, the tub is a p-tub or an n-tub.
In another embodiment, the semiconductor device further comprises a gate, a third active area, and a field oxide. The third active area is not in contact with the interconnect, and the field oxide is formed between the second and third active areas. In one aspect of this embodiment, the gate contacts the first and third active areas.
In yet another embodiment, the semiconductor device further comprises a second gate in contact with the second active area. In an alternative embodiment, the semiconductor device further comprises a dielectric formed over the gate, the field oxide, and the first, second and third active areas. In one aspect, the dielectric has dummy plugs formed over the first and second active areas and in contact with the interconnect.
In still another embodiment, the semiconductor device further comprises a dielectric formed over the first and second active areas. The dielectric has conductive dummy plugs that are formed over the first and second active areas and that are in contact with the interconnect. In one aspect of the present invention, the interconnect is electrically connected to a current source. In another aspect, the semiconductor device may be a DRAM device, a FLASH device, a ROM device, or an SRAM device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5283454 (1994-02-01), Cambou
patent: 5384475 (1995-01-01), Yahata
patent: 5666002 (1997-09-01), Yamamoto et al.
patent: 6268248 (2001-07-01), Mehrad
Agere Systems Inc.
Kang Donghee
Loke Steven
LandOfFree
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