Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2006-08-22
2006-08-22
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S600000, C327S149000
Reexamination Certificate
active
07096376
ABSTRACT:
In a semiconductor integrated circuit device (700) in which variation in a minimum propagation time of a transmission signal from a source node (SN) to a destination node (DN) is sufficiently large, relative to a clock period (T) at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node (DN) a plurality of clocked elements (8000to8003) are connected in series between the source and destination nodes for causing a shift signal (SS0to SS4), representing the transmission signal present at the source node (SN) in a first clock cycle, to be shifted from the source node (SN) to the destination node (DN) through the series of clocked elements (8000to8003) one clocked element (800i) per predetermined number of clock cycles. The series of clocked elements (8000to8003) is connected and arranged such that variation (vi) in a propagation time of the shift signal (SSi) from one clocked element (800i-1) to the next clocked element (800i) is sufficiently small, relative to the clock period (T), that a clock cycle in which the shift signal (SSi) reaches the next clocked element (800i) does not vary, whereby the shift signal (SS4) always reaches the destination node (DN) a fixed number of clock cycles after the first clock cycle.
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English language Search Report for United Kingdom Application GB 0120717.4.
Cao Chun
Fujitsu Limited
Staas & Halsey , LLP
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