Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2006-04-11
2006-04-11
Everhart, Caridad (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S014000
Reexamination Certificate
active
07026647
ABSTRACT:
A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
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patent: 6028324 (2000-02-01), Su et al.
patent: 6429452 (2002-08-01), Jarvis
patent: 2004/0153275 (2004-08-01), Wang
Huang Chien-Chang
Huang Chin-Ling
Jiang Bo Ching
Ting Yu-Wei
Wu Tie Jiang
Everhart Caridad
Nanya Technology Corporation
Quintero Law Office
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