Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2005-07-12
2005-07-12
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S104000, C710S118000, C710S309000, C711S167000
Reexamination Certificate
active
06917994
ABSTRACT:
An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.
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Maone Alessandro Francesco
Perroni Maurizio Francesco
Carlson David V.
Jorgenson Lisa K.
Myers Paul R.
Phan Raymond N
Seed IP Law Group PLLC
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