Stack chip package structure

Details Stack chip package structure Stack chip package structure

2005-07-19

2005-07-19

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S687000, C257S681000

Reexamination Certificate

active

06919628

ABSTRACT:
A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.

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patent: 6469380 (2002-10-01), Sorimachi et al.
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patent: 6737755 (2004-05-01), McLellan et al.
patent: 2002/0096754 (2002-07-01), Chen et al.
patent: 2003/0127722 (2003-07-01), Nakaoka et al.

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