Device and a method for storing data and corresponding error-cor

Details Device and a method for storing data and corresponding error-cor Device and a method for storing data and corresponding error-cor

1995-10-31

1999-08-24

Grant, William

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714702, 714755, 714758, 714761, 714764, 714766, 714765, 714711, 365149, 365201, 320122, G11C 2900

Patent

active

059420049

ABSTRACT:
The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

REFERENCES:
patent: 3644898 (1972-02-01), Post
patent: 4335459 (1982-06-01), Miller
patent: 4691318 (1987-09-01), Entenman
patent: 4958352 (1990-09-01), Noguchi et al.
Kalter, Howard L. et al., "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1118-1127.
"ECC in 512 Bytes Sector Nand-Type Flash Eprom," IBM Technical Disclosure Bulletin, vol. 35, No. 7, Dec. 1992, pp. 131-132.

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