Fishing – trapping – and vermin destroying
Patent
1989-07-11
1990-08-14
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437192, 437193, 437200, 437246, 357 71, H01L 21283
Patent
active
049487558
ABSTRACT:
A method is disclosed for fabricating a semiconductor integrated circuit which includes the selective deposition of a metal, such as tungsten, into a contact opening formed in a dielectric layer, followed by the deposition of a thin silicon layer over the dielectric and metal-filled opening and the deposition of a second dielectric layer over the thin silicon layer. An opening or trench is formed in the upper second dielectric layer using the silicon as an etch stop, and a metal such as tungsten is selectively deposited to fill the trench wherever the exposed silicon is present. In one embodiment of the invention, prior to the filling of the trench, the exposed silicon is reacted with a blanket layer of a metal to form a metal silicide layer at the lower surface of the trench.
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patent: 4814285 (1989-03-01), Matlock et al.
Moriya, T. et al., "A Planar Metallization Process . . . ", IEEE IEDM Tech. Dig., 1983, pp. 550-553.
Hearn Brian E.
Quach T. N.
Standard Microsystems Corporation
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