Determining timing associated with an input or output of an...

Details Determining timing associated with an input or output of an... Determining timing associated with an input or output of an...

2006-07-20

2009-02-17

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S725000, C714S736000

Reexamination Certificate

active

07493543

ABSTRACT:
Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

REFERENCES:
patent: 6541994 (2003-04-01), Masuda
patent: 7321249 (2008-01-01), Watanabe et al.
patent: 7406646 (2008-07-01), Sato et al.

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