Determining edge relationship between clock signals

Details Determining edge relationship between clock signals Determining edge relationship between clock signals

2007-12-04

2007-12-04

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11072871

ABSTRACT:
First and second clock signals are provided to first and second sequential circuits, where the first and second clock signals are inversely coupled to logic high and low levels for clocking of the first and second sequential circuits. A third sequential circuit is clocked responsive to a first output from the first sequential circuit and receives first signature data. A fourth sequential circuit is clocked responsive to a second output from the second sequential circuit and receives second signature data. A third output from the third sequential circuit is monitored responsive to the first signature data and the first output. A fourth output from the fourth sequential circuit is monitored responsive to the second signature data and the second output. Whether the first clock signal and the second clock signal are phase aligned may be determined responsive to the third output and the fourth output.

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