Detection circuit and method for AC coupled circuitry

Details Detection circuit and method for AC coupled circuitry Detection circuit and method for AC coupled circuitry

2011-01-25

2011-01-25

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07877652

ABSTRACT:
Standardized scan cell logic is enabled to test board-level and circuit-level AC interfaces built into integrated CMOS circuits by verification of high-speed AC coupled non-CMOS logic level signals driven onto non-CMOS logic level AC coupled interconnects in those circuits.

REFERENCES:
patent: 4839878 (1989-06-01), Inoue
patent: 5673130 (1997-09-01), Sundstrom et al.
patent: 6662134 (2003-12-01), Moore
patent: 6691269 (2004-02-01), Sunter
patent: 6763486 (2004-07-01), Lai et al.
patent: 6877121 (2005-04-01), Srinivasaiah et al.
patent: 2003/0229835 (2003-12-01), Whetsel
IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.1-1990.

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