Detecting bit errors in a communications system

Details Detecting bit errors in a communications system Detecting bit errors in a communications system

2006-01-03

2006-01-03

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

Reexamination Certificate

active

06983403

ABSTRACT:
Error codes output from a serializer/deserializer in a node of a communications network are detected by error decode logic that assumes that each new error occurrence reflects a one bit error in the word giving rise to the error code. Each error occurrence is then counted. When the error count reaches a predetermined limit (e.g., 250 errors), the total bit count required to accumulate the 250 errors is then determined. The total bits can be determined based on a clock count (time). The BER is then calculated based upon the fixed error limit and the total bit count. This BER is then reported and used to determine the health of the network.

REFERENCES:
patent: 5623497 (1997-04-01), Shimawaki et al.
patent: 6076175 (2000-06-01), Drost et al.
“Multi-Gigabit Interconnect Chip”, Vitesse, Semiconductor Corporation data sheet, Oct. 23, 2000. pp. 1-38.

Affiliated with

Also associated with

Rating

Detecting bit errors in a communications system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Detecting bit errors in a communications system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Detecting bit errors in a communications system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3594197