Design verification

Details Design verification Design verification

2007-09-11

2007-09-11

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10908786

ABSTRACT:
A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.

REFERENCES:
patent: 6031986 (2000-02-01), Milsom
patent: 6240375 (2001-05-01), Sonoda
patent: 6415421 (2002-07-01), Anderson et al.
patent: 6425113 (2002-07-01), Anderson et al.
patent: 6532439 (2003-03-01), Anderson et al.
patent: 6544699 (2003-04-01), Kim et al.
patent: 6622289 (2003-09-01), Saunders et al.
patent: 6941530 (2005-09-01), Joshi et al.
patent: 2003/0237064 (2003-12-01), White et al.

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