Design structure to reduce power consumption within a clock...

Details Design structure to reduce power consumption within a clock... Design structure to reduce power consumption within a clock...

2007-09-06

2010-06-08

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C326S093000, C327S141000, C327S142000, C327S143000

Reexamination Certificate

active

07735038

ABSTRACT:
A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

REFERENCES:
patent: 2003/0131270 (2003-07-01), Abernathy et al.
patent: 2005/0254585 (2005-11-01), Adams et al.
Li, et al. Deterministic Clock Gating for Microprocessor Power Reduction, ECE Department, Purdue University.

Affiliated with

Also associated with

Rating

Design structure to reduce power consumption within a clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design structure to reduce power consumption within a clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design structure to reduce power consumption within a clock... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4247941