Design structure for a current control mechanism for power...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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C326S083000, C326S112000, C326S098000, C716S030000

Reexamination Certificate

active

07471114

ABSTRACT:
A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

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Kim, C.H., et al., “A Process Variation Compensating Technique for Sub-90 nm Dynamic Circuits”, VLSI Circuits 2003, Digest of Technical Papers, 2003 Symposium on Jun. 12-14, 2003, pp. 205-206.
Kursun, E.G. et al., “Domino Logic With Dynamic Body Biased Keeper”, Solid-State Circuits Conference 2002, ESSCIRC 2002, Sep. 24-26, 2002, pp. 675-678.

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