Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
1999-02-08
2001-02-06
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S024000, C326S083000
Reexamination Certificate
active
06184704
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to CMOS (Complementary Metal Oxide Semiconductor) digital input circuits with compensation for manufacturing process variation as it affects circuit characteristics.
BACKGROUND OF THE INVENTION
A basic digital input circuit contains two or more chained inverter stages. In order to guarantee enough tolerance to noise, an input low voltage, Vil, and an input high voltage, Vih, switch levels at the input are specified. Modern integrated circuit requirements have pushed the two specifications closer and closer. For example, in current digital circuits using a 3.3V supply voltage, Vdd, one often finds Vil=0.3 Vdd and Vih=0.4 Vdd, resulting in a window of 0.1 Vdd which is only 0.33V.
However, the variation of the integrated circuit manufacturing process may introduce a shift in the input switching voltage level, or toggle voltage, Vtgl. We define the toggle voltage, Vtgl, as the input voltage at which the output voltage of an inverter chain is equal to 0.5 Vdd. The purpose of defining Vtgl is as the input voltage sweeps, the output of an inverter changes very steeply when flipping from one state to another state. The extent of the Vtgl variation range is mainly dependent on manufacturing process variations. Its magnitude must lie within the Vil and Vih range. The manufacturing process variation, therefore, reduces the noise margin of the whole circuit.
Three US patents are known which deal with the subject of circuit compensation for manufacturing process variation.
U.S. Pat. No. 5,111,081 (Atallah) provides a CMOS inverter in which variations in process are compensated for by varying the W/L ratio of the inverter FET devices by means of switching in selected other FETs in parallel with the inverter FET devices.
U.S. Pat. No. 4,975,599 (Petrovick, Jr. et al.) provides a technique for compensating for process variation in CMOS driver circuits using 5-transistor compensation circuits for control of each output device in the driver. In this patent the compensation is intended to stabilize the speed of operation of the driver.
U.S. Pat. No. 5,434,532 (Thiel) discloses a voltage reference circuit including CMOS devices for compensation of process variation in transistor circuits.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an improved design of CMOS digital input circuits when manufacturing process variations change the operational characteristics of the individual transistor elements in the circuit.
Another object of this invention is to provide an integrated CMOS digital input circuit whose operation has a reduced sensitivity to manufacturing process variations.
Another object of this invention is to provide an integrated CMOS digital input circuit which can tolerate the presence of larger noise levels.
Another object of this invention is to provide an integrated CMOS digital input circuit which has an increased tolerance of smaller input voltage margins resulting from lower supply voltage.
Another object of this invention is the increased ability of an integrated CMOS digital input circuit to operate reliably with a low voltage supply when manufacturing process variations reduce the input voltage margins.
These objects have been achieved by providing resistive compensation devices in series with the P-type and the N-type CMOS transistors in the first stage of a multistage digital input circuit. These resistive devices can be implemented by means of resistors or by means of MOSFET devices which provide the required resistive function. The preferred embodiment uses the MOSFET implementation of the resistive devices. The function of the resistive compensating devices is to change the transfer function of the first stage so as to reduce the excursion of input voltage switching levels resulting from manufacturing process variations, thereby reducing the switching uncertainty range and increasing the noise margin of the input circuit.
The present invention is applicable to different types of integrated CMOS multistage input circuits. The preferred embodiments describe two possible implementations, one being a multistage CMOS inverter chain where the first stage is an inverter, and the other using a Schmitt trigger as the first stage of the inverter chain.
REFERENCES:
patent: 4578600 (1986-03-01), Magee
patent: 4806801 (1989-02-01), Argade et al.
patent: 4975599 (1990-12-01), Petrovick, Jr. et al.
patent: 5111081 (1992-05-01), Attallah
patent: 5175445 (1992-12-01), Kinugasa et al.
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5416366 (1995-05-01), Adachi
patent: 5434532 (1995-07-01), Thiel
patent: 5602496 (1997-02-01), Mahmood
patent: 5959473 (1999-09-01), Sakuragi
Hisano, U.S. Statutory Invention Registration H8O2, Jul. 1990.
Hu Yu David
Oei Chan Chee
Wang Hongwei
Ackerman Stephen B.
Saile George O.
Santamauro Jon
Tritech Microelectronics
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