Design layout preparing method

Details Design layout preparing method Design layout preparing method

2007-03-20

2007-03-20

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11012491

ABSTRACT:
There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

REFERENCES:
patent: 6507931 (2003-01-01), Kotani et al.
patent: 6576147 (2003-06-01), Mukai
patent: 2003/0093767 (2003-05-01), Murai et al.
patent: 2003/0115569 (2003-06-01), Ikeuchi
patent: 2004/0015794 (2004-01-01), Kotani et al.
patent: 2002-026126 (2002-01-01), None
patent: 2002-131882 (2002-05-01), None
patent: 2003-303742 (2003-10-01), None

Affiliated with

Also associated with

Rating

Design layout preparing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design layout preparing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design layout preparing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3740800