Design flow for shrinking circuits having non-shrinkable IP...

Details Design flow for shrinking circuits having non-shrinkable IP... Design flow for shrinking circuits having non-shrinkable IP...

2007-05-30

2009-12-29

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07640520

ABSTRACT:
A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.

REFERENCES:
patent: 5477467 (1995-12-01), Rugg
patent: 5493510 (1996-02-01), Shikata

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