Deposition stop time detection apparatus and methods for...

Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed

Reexamination Certificate

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C438S018000, C257SE21520, C257SE21530

Reexamination Certificate

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07122387

ABSTRACT:
A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

REFERENCES:
patent: 5290396 (1994-03-01), Schoenborn et al.
patent: 5400209 (1995-03-01), Moslehi
patent: 5960254 (1999-09-01), Cronin
patent: 6022465 (2000-02-01), Ting et al.
patent: 6277263 (2001-08-01), Chen
patent: 6391166 (2002-05-01), Wang
patent: 2003/0000840 (2003-01-01), Kimura et al.

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