Deposition of low dielectric constant thin film without use...

Details Deposition of low dielectric constant thin film without use... Deposition of low dielectric constant thin film without use...

1999-12-30

2001-12-18

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S513000, C438S765000, C438S772000, C438S778000, C438S787000, C438S788000, C438S790000

Reexamination Certificate

active

06331494

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method and precursors for forming low dielectric constant insulator material in integrated circuits.
2. Statement of the Problem
As semiconductor technology advances, circuit elements and interconnections on wafers or silicon substrates become increasingly more dense. As a result of the continuing trend toward higher device densities, parasitic interdevice currents are increasingly problematic. In order to prevent unwanted interactions between these circuit elements, insulator-filled gaps, or trenches, located between active circuit devices and metallized interconnect layers are provided to physically and electrically isolate the elements and conductive lines. However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, typically defined as the gap depth divided by the gap width. As the gaps become narrower, parasitic capacitance increases, and filling the gaps with insulating material becomes more difficult. This can lead to unwanted voids and discontinuities in the insulating, or gap-fill, material.
For example, in metal-oxide-semiconductor (“MOS”) technology, it is necessary to provide an isolation structure that prevents parasitic channel formation between adjacent devices, such devices being primarily NMOS and PMOS transistors or CMOS circuits. Trench isolation technology has been developed in part to satisfy such insulation needs. Refilled trench structures essentially comprise a recess formed in the silicon substrate that is refilled with a dielectric insulating material. Such structures are fabricated by first forming submicron-sized trenches in the silicon substrate, usually by a dry anisotropic etching process. The resulting trenches typically display a steep side-wall profile. The trenches are subsequently refilled with a dielectric, such as silicon dioxide, typically by a chemical vapor deposition (“CVD”) technique. They are then planarized by an etchback process so that the dielectric remains only in the gap, its top surface level with that of the silicon substrate. The resulting filled-trench structure functions as a device isolator having excellent planarity and potentially high aspect ratio beneficial for device isolation. Refilled trench isolation can take a variety of forms depending upon the specific application; they are generally categorized in terms of the trench dimensions: shallow trenches (<1 &mgr;m), moderate depth trenches (1 &mgr;m to 3 &mgr;m), and deep, narrow trenches (>3 &mgr;m deep, <2 &mgr;m wide). Shallow Trench Isolation (STI) is used primarily for isolating devices of the same type in increasingly dense MOS circuits. STI provides a high degree of surface planarity.
Similar isolation techniques are used to separate closely spaced circuit elements that have been formed on or above a semiconductor substrate during integrated circuit fabrication. The circuit elements may be active devices or conductors, and are isolated from each other by refilled “gaps”.
The basic trench, or gap, isolation process is, however, subject to drawbacks, one of these being void formation in the gap during dielectric gap fill. Such voids are formed when the gap-filling dielectric material forms a constriction near the top of the gap, preventing deposition of the material into the gap interior. Such voids compromise device isolation, as well as the overall structural integrity. Unfortunately, preventing void formation during gap fill often places minimum size constraints on the gaps themselves, which may compromise device packing density or device isolation.
Silicon dioxide is formed by conventional CVD techniques by mixing a gaseous oxidizer (e.g., N
2
O), silane (SiH
4
) and inert gases, such as argon, and energizing the mixture in a reactor so that the oxygen and silane react to form silicon dioxide on a wafer substrate. Currently, plasma-enhanced chemical vapor deposition (“PECVD”) processes are used to fill gaps with silicon oxide material. In PECVD processes, a plasma of ionized gas is formed in the CVD plasma reactor. The plasma energizes the reactants, enabling formation of the desired silicon dioxide at lower temperatures than would be possible by adding only heat to the reactor system. In a typical plasma-enhanced CVD (“PECVD”) process, the plasma is a low pressure reactant gas discharge that is developed in a radio-frequency (“rf”) field. The plasma is an electrically neutral ionized gas in which there are equal number densities of electrons and ions. At the relatively low pressures used in PECVD, the electron energies can be quite high relative to heavy particle energies. The high electron energy increases the density of dissociated reactants within the plasma available for reaction and deposition at the substrate surface. The enhanced supply of reactive free radicals in the PECVD reactor enables the deposition of dense, good quality films at lower temperatures (e.g., 400° C.) and at faster deposition rates (30 nm/min to 40 nm/min) than typically achieved using only thermally-activated CVD processes (10 nm/min to 20 nm/min).
In addition to silane (SiH
4
), other silicon-containing precursors have been used to form silicon dioxide, including disilane (S
2
H
6
) and tetraethoxysilane (“TEOS”). All of these processes require mixing the silicon-containing reactant with an oxidizing gas reactant, such as oxygen gas (O
2
), ozone (O
3
), nitrous oxide (N
2
O), nitrogen dioxide (NO
2
) or carbon dioxide (CO
2
).
The capacitance across a gap is governed by the formula
C=∈kA/t,
where C is the capacitance, ∈ is the dielectric constant of the gap fill material, k is a constant, A is the area of the gap (i.e., the area of the side of the circuit element forming the gap), and t is the thickness or width of the gap. As gap widths decrease with increasing density, the capacitance across the dielectric gap fill material increases. Thus, as integrated circuits become increasingly dense, decreasing t, it is necessary to lower the dielectric constant of the gap fill material to reduce cross-talk, capacitive coupling and resulting speed degradation, and power consumption. To compensate for smaller gap dimensions, it is known to substitute dielectric materials having dielectric constants lower than silicon dioxide. It is known in the prior art to form halogen-doped silicon dioxide. For example, fluorinated silicon dioxide films possess a dielectric constant of approximately 3.2, whereas typical CVD-SiO
2
has a dielectric constant of about 3.9. It is also known to use multilayer or “sandwich” gap-fill material, including structures comprising a silicon dioxide layer and a non-silicon carbon-based layer or a polymer layer. Although these structures may possess an overall dielectric constant lower than silicon dioxide, their fabrication processes are slow, complex and expensive, and they are limited with respect to aspect ratios achieved.
Design feature widths of integrated circuit devices are currently approaching 0.25 &mgr;m, or 250 nm. To achieve corresponding overall circuit density, gap dimensions of approximately 100 nm to 400 nm gap width range and 300 nm to 1000 nm gap depth range are desired, having corresponding range of aspect ratios of 2 to 6. Furthermore, because the gap is so thin, the insulating gap material should have a dielectric constant of 3.3 or less.
A gap opening of 500 nm or less is too small for depositing material using conventional CVD and PECVD methods. Also, as the deposition of gap-filling material proceeds, the gap opening becomes smaller, making it more difficult to fill and creating the risk of void formation. Currently, high density plasma (“HDP”) CVD is used to fill high aspect ratio gaps. Also, using HDP-CVD, it is usually possible to deposit silicon oxide films at lower temperatures (e.g., 150° C. to 250° C.) than in a PECVD process. Typical HDP-CVD processes use a gas mixture containing oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric depo

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