Depletion mode MOS capacitor with patterned V.sub.t implants

Details Depletion mode MOS capacitor with patterned V.sub.t implants Depletion mode MOS capacitor with patterned V.sub.t implants

1997-10-08

1999-11-16

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257407, H01L 2936, H01L 2978

Patent

active

059863145

ABSTRACT:
A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

REFERENCES:
patent: 4570331 (1986-02-01), Eaton, Jr. et al.
patent: 4888631 (1989-12-01), Azuma et al.
patent: 5286991 (1994-02-01), Hui et al.
patent: 5424566 (1995-06-01), Nishihara

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