Depleted sidewall-poly LDD transistor

Details Depleted sidewall-poly LDD transistor Depleted sidewall-poly LDD transistor

1998-03-26

2001-10-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S303000, C438S304000, C438S596000, C438S976000

Reexamination Certificate

active

06300207

ABSTRACT:

TECHNICAL FIELD
The present invention relates to metal oxide semiconductor field-effect transistors (MOSFETs), and, more particularly, to lightly doped drain (LDD) structures. Specifically, the present invention relates to an improved MOSFET structure employing LDD technology which significantly reduces drain-to-gate overlap capacitance.
BACKGROUND ART
Attempts continue to shrink the dimensions for fabricating metal oxide semiconductor (MOS) transistors. Devices having sub-micrometer dimensions permit closer placement of devices, thereby increasing the density of devices on a chip and also increasing device operating speed.
A conventional MOS transistor which is formed in a semiconductor substrate includes a drain region and a source region separated by a channel region. The channel region resides beneath a gate comprising a gate oxide and a gate electrode formed thereon. A conducting channel is induced in the channel region by an electric field established between the gate and the semiconductor substrate.
To fabricate an MOS transistor, the drain region and the source region are formed in the semiconductor substrate, which has a first conductivity (e.g., p-type), by doping selected regions of the semiconductor substrate. Doping is performed such that the drain region and the source region have a second conductivity (e.g., n-type) that is opposite to the first conductivity. In the case where the semiconductor substrate comprises silicon, the gate electrode and the gate oxide may comprise, for example, polysilicon (“poly”) and silicon dioxide, respectively.
Hot-carrier degradation is a major limitation of scaling down the dimensions of MOS devices; hot-carrier degradation results from the high electric fields encountered in submicrometer MOSFETs. Although an energy barrier separates the gate oxide from the semiconductor substrate, electrons (known as“hot carriers”) that have enough energy to overcome this energy barrier are injected into the gate oxide. The injection of these“hot carriers” causes damage to the gate oxide, which affects the performance of the MOS device. Hot-carrier degradation refers to the performance degradation that results from this damage to the gate oxide.
Hot-carrier degradation is reduced by the structure of lightly doped drain (LDD) transistors. The key feature of LDD technology is the insertion of a graded, or more gently profiled, lightly doped drain region, such as an n
−
drain region, between the channel region and a heavily doped part of the drain region, such as an n
30
drain region. As is conventional, the term“drain” may be used generically and can apply to both the drain and the source. Accordingly, in LDD transistors, a graded, or more gently profiled, lightly doped source region, such as an n
31
source region, is inserted between the channel region and a heavily doped part of the source region, such as an n
30
source region. The source-side LDD is formed simultaneously with the drain-side LDD. A voltage is sustained mainly across the drain-side LDD. The lightly doped drain region sustains the drain voltage over a longer area. Similarly, the lightly doped source region sustains a source voltage over a longer area. Thus, the peak electric field at the drain region and source region is reduced.
There are many types of LDD transistors presently in use which reduce the hot-carrier degradation inherent in MOSFETs. For example, performance degradation due to hot carrier damage in MOS transistors can be improved by making LDD regions (i.e., the lightly doped drain region and the lightly doped source region) fully overlapped by the gate electrode. Such an approach is demonstrated by gate over-lapped drain (GOLD) structures as well as inverse-T gate LDD (ITLDD) structures. These conventional fully overlapped LDD structures, however, suffer from a high capacitance between the gate and drain region as well as between the gate and source region. Such capacitance is conventionally known in the art as drain-to-gate overlap capacitance. In conventional fully overlapped LDD structures, the drain-to-gate overlap capacitance typically corresponds to the value of capacitance across the gate oxide. This value of capacitance depends on the thickness of the gate oxide. Disadvantageously, a high drain-to-gate overlap capacitance can seriously limit AC circuit performance.
Thus, what is needed is an improved MOSFET structure that employs LDD regions that are fully overlapped by gate polysilicon but that has a drain-to-gate overlap capacitance significantly reduced in comparison to conventional fully overlapped LDD transistors.
DISCLOSURE OF INVENTION
In accordance with the invention, a metal oxide semiconductor transistor formed in a semiconductor substrate having a first conductivity is provided. The metal oxide semiconductor transistor comprises:
(a) a heavily doped source region, a lightly doped source region, a heavily doped drain region, and a lightly doped drain region, each having a second conductivity opposite the first conductivity;
(b) a channel region in the semiconductor substrate having the first conductivity and separating the heavily doped source region and the heavily doped drain region, the lightly doped source region located adjacent the heavily doped source region and extending to the channel region, the lightly doped drain region located adjacent the heavily doped drain region and extending to the channel region;
(c) a gate oxide covering at least the channel region, the lightly doped source region, and the lightly doped drain region; and
(d) a gate electrode formed on the gate oxide comprising (i) a main gate region formed over the channel region comprising doped polysilicon and having two sidewalls and (ii) a depleted sidewall polysilicon spacer comprising depleted polysilicon formed adjacent each of the two sidewalls and at least partially overlapping the lightly doped source region and the lightly doped drain region, the combination of the depleted sidewall polysilicon spacers and the main gate region fully overlapping the lightly doped source region and the lightly doped drain region.
The method for constructing the metal oxide semiconductor transistor of the present invention comprises the following steps:
(a) forming a gate oxide on the semiconductor substrate covering at least the channel region, the lightly doped drain region, and the lightly doped source region;
(b) depositing and patterning a layer of polysilicon on the gate oxide thereby forming a main gate region over the channel region having two sidewalls;
(c) forming a mask on the semiconductor substrate which includes two disposable spacers each of which is adjacent one of the sidewalls;
(d) exposing the main gate region and portions of the semiconductor substrate to a first ion implant and subsequent anneal, thereby doping the main gate region and forming the heavily doped source region and the heavily doped drain region;
(e) removing the disposable spacers;
(f) exposing the semiconductor substrate to a second ion implant and subsequent anneal, thereby forming the lightly doped source region and the lightly doped drain region below where the disposable spacers were previous located; and
(g) providing a depleted sidewall polysilicon spacer comprising depleted polysilicon adjacent each of the two sidewalls by depositing and patterning undoped polysilicon such that the lightly doped source region and the lightly doped drain region are completely fully overlapped by the combination of the depleted sidewall polysilicon spacers and the main gate region, the undoped polysilicon covering a portion of the lightly doped source region and a portion of the lightly doped drain region.
The depleted sidewall polysilicon spacers which overlap the lightly doped regions, i.e., the lightly doped source region and the lightly doped drain region, provide the advantages of conventional fully overlapped LDD transistors. In particular, performance degradation due to damage induced by hot carrier injection into the gate oxide is improved because the lightly doped regions lie beneath the gate po

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