Delineation pattern for epitaxial depositions

Details Delineation pattern for epitaxial depositions Delineation pattern for epitaxial depositions

1996-08-15

2001-01-09

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S705000, C438S719000, C438S733000, C216S039000, C216S062000, C117S095000, C117S097000

Reexamination Certificate

active

06171966

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to method for use in semiconductor fabrication and, in particular, to method for forming a delineation step pattern for epitaxial depositions by which pattern wash-out is substantially reduced.
BACKGROUND OF THE INVENTION
One technique for manufacturing semiconductor devices involves depositing epitaxial layers on a silicon wafer. The use of epitaxial layers provides several advantages, including the ability to alter dopant levels and types. Additionally, one may use a buried layer, also called a diffused subcollector, that is precisely located beneath an active device formed by later fabrication steps. Such precise location requires registration between the buried layer and the active device and the present invention provides a method for registrating these later device fabrication steps with the buried layer.
FIG. 1
illustrates a conventional semiconductor structure
2
comprising a monocrystalline silicon wafer substrate
4
on which an oxide mask
6
has been deposited. Substrate
4
has a <100> crystallographic orientation. As shown in
FIG. 1
, gap
8
in oxide mask
6
exposes a portion
10
of surface
12
of substrate
4
. A doped region
14
is created at gap
8
by conventional means, typically by diffusing or implanting dopant into the exposed, oxide-free surface
10
. The dopant is preferably driven into substrate
4
at an elevated temperature, such as 900° C-1200° C.
FIGS.
2
-
4
A illustrate further fabrication steps in accordance with the prior art. As shown in
FIG. 2
, a delineation oxide layer
16
is formed on top of doped region
14
, delineation oxide layer
16
is typically about 1000 Å to 4000 Å A thick.
FIG. 3
illustrates the results produced by an oxide stripping procedure in which both oxide mask
6
and delineation oxide layer
16
have been stripped away from substrate
4
. As shown in
FIG. 4
, after the oxide stripping procedure, the periphery of doped region
14
is defined by oxidation delineation step
18
. As is seen in
FIG. 4
, step
18
has a quarter-circle or fillet shape.
One problem particular to substrates having a <100> crystal orientation is that, as epitaxial layers are deposited, the distinctiveness of the delineation step softens or is obscured; this softening or obscuring of the delineation step is often referred to as pattern wash-out. A washed-out delineation step is illustrated in FIG.
4
A. The problem caused by the indistinct nature of the washed-out delineation step is that accurate registration with periphery
22
of doped region
14
becomes difficult or impossible.
SUMMARY OF THE INVENTION
The present invention is directed to an improved method for forming a delineation step pattern for epitaxial depositions by which pattern wash-out is substantially reduced.
The improved delineation pattern for epitaxial depositions is provided by first forming a mask on a single-crystal silicon substrate leaving a region (or regions) of the substrate exposed. The mask is typically an oxide, but it can also be a composite of oxide and nitride. The exposed region is then doped, or implanted, to create a doped region. Next, this doped region is subjected to a drive-in procedure in a drive-in furnace or to an annealing procedure in a rapid thermal processing (RTP) unit. Next, the mask used to define the outline of the doped region is also used as a mask during an anisotropic vertical etch step. This provides a delineation pattern corresponding to the periphery of the etched region. Advantageously, in accordance with the present invention, the periphery of the etched region, that is the delineation step, has a squared-off characteristic, i.e., the improved delineation step provides a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. Subsequent process steps typically include removing the mask and forming one or more epitaxial layers over the substrate and the vertically etched region.
It is important that the anisotropic vertical etching step provides an essentially damage-free etched surface in order to minimize unfavorable device performance characteristics that result from propagation of damage by subsequent epitaxial growth steps. Further, it is also important that the vertical etching step be essentially residue-free so that undesirable by-products are not left in the area that will subsequently be subjected to epitaxial processing steps. This latter requirement is, however, tempered by the fact that subsequent epitaxial processing steps occur at high temperatures in a reducing ambient (typically hydrogen) environment which tends to eliminate any such residues that may be created.
The importance of the squared-off shape of the delineation step results from the fact that growth rate during epitaxial deposition is dependent upon the crystallographic orientations of the monocrystalline substrate upon which the epitaxial deposition takes place. The delineation step created by conventional procedures provides a continuum of crystallographic orientations for the epitaxial deposition along the delineation step. This range of crystallographic orientations results in a range of growth rates for the epitaxial layer or layers grown on the delineation step. The different growth rates create a softening or pattern wash-out at the delineation step. However, in accordance with the present invention, anisotropic vertical etching of the delineation pattern produces a squared-off or effectively right-angle step ideally providing only two crystallographic orientations: preferably a <110> orientation along the first or vertical step wall extending from the surface of the substrate and a <100> orientation along the second or horizontal step wall bounding the etched region. The presentation of only these two different crystallographic orientations to the epitaxial layer effectively maintains the sharp contour of the squared-off or right-angle delineation step even after one or more epitaxial layers have been grown on the substrate. This minimizes wash-out of the delineation step as occurs after creating conventional buried layer patterns formed by oxidation techniques.
Other features and advantages of the invention will appear from the description in which the preferred embodiment and method have been disclosed in conjunction with the accompanying drawings.


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Enomoto, T. et al “Pattern washout effect in epitaxial process of iintegrated circuit fabrication” Japanese J. Appl. Phys., vol. 8, No. 11, pp. 1301-1306, Nov. 1969.*

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