Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2004-12-31
2008-03-18
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S501000, C713S503000
Reexamination Certificate
active
07346795
ABSTRACT:
In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.
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Klowden Daniel S.
Kumar S. Reji
Panikkar Adarsh
Abbaszadeh Jaweed A
Intel Corporation
Lee Thomas
Pedigo Philip A.
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