Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2000-04-20
2001-06-12
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000
Reexamination Certificate
active
06247137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to clocking data in digital systems. More specifically, the present invention relates to the determination of phase-based relationships between two clocks having the same frequency, but initially unknown phase-based relationships.
DESCRIPTION OF THE RELATED ART
In the art of digital signal processing, which of course includes the art of computing, it is common to clock data from one integrated circuit (the sending IC) to another IC (the receiving IC) using a clock signal generated externally from both ICs. Often the sending IC will also produce a strobe signal that is delayed by ¼ of a cycle from the internal clock of the sending IC so that the data transmitted by the sending IC can be validated at the receiving IC. While the data from the sending IC is easily captured at the receiving IC using the strobe signal produced by the sending IC, the receiving IC must then shift the data from the clock domain of the sending IC to its own clock domain to continue processing the data. While the clocks within the sending and receiving ICs are the same frequency, the phase relationship between the clocks is initially unknown because of clock skew, the ¼ cycle delay, and other factors.
One prior art method of shifting data from one clock domain to another is to sequentially clock data from the sending IC into a series of flip flops using a round robin scheme, and holding each data bit at a flip flop for a longer period of time. For example, consider a strobe signal from the sending IC that indicates valid data on both the rising and falling edges (which will generically be referred to as validation edges), and a single data input pad coupled to four flip flops. Each flip flop is clocked by a signal running at ¼ the frequency of the validation edges of the strobe signal from the sending IC, and the clock of each flip flop is delayed by one validation edge with respect the flip flop logically adjacent to it. In such an arrangement, the first, fifth, and ninth bits will be received at the first flip flop, the second, sixth, and tenth bits will be received at the second flip flop, and so on. Since each bit is held within each flip flop for four validation edges, it is easier to select one of the clock edges of the receiving IC's clock to validate the incoming data bit and transfer the data bit from the sending IC's clock domain to the clock domain of the receiving IC.
While using such a round robin scheme eases the problem of transferring the data bit from the sending IC's clock domain to the clock domain of the receiving IC, the receiving IC must still have some method of determining which flip flop to read data from for any given clock cycle. In the example above, for a given validation edge of the receiving ICs clock, the data is typically more centered and best validated at one of two possible flip flops. Accordingly, a select signal is required to determine which flip flop to read for any given validation edge of the clock of the receiving IC.
In the prior art, this select signal was typically selected using a master IC. The master IC contained a series of registers that stored the proper orientation of select signals for the ICs on the board. A designer would design the logic circuit, and when the design was nearing conclusion, would perform timing simulations for the complete system. Based on the timing simulations, the proper values would be loaded into the registers of the master IC to provide the proper select signal orientation to the other ICs. If it turned out that the simulations were not accurate, or subsequent modifications were made to the board which altered clock skew, the select signal orientations could easily be changed by reloading the registers of the master IC.
While the master IC works well, programming it requires extra simulation steps and subsequent debugging. In addition, using a master IC can consume many I/O pins. Note that a select signal is required for each strobe signal provided by another IC. Therefore, if an IC is designed to receive strobe signals from twelve other ICs, twelve I/O pins are required. Unfortunately, in the art of integrated circuit design increases in transistor density are not matched by corresponding increases in I/O pin density. It is becoming increasing difficult to dedicate so many I/O pins to select signals.
A solution to this problem was disclosed by Paul L. Rogers in co-pending U.S. application Ser. No. 09/365,055, which was filed on Jul. 30, 1999, is entitled “A Method and Apparatus for Automatically Determining the Phase Relationship Between Two Clocks Generated from the Same Source”, is assigned to the same assignee as the present application, and is incorporated by reference above. This application discloses a phase detection circuit that compares the initial phase of the select signal in the clock domain of the receiving IC with one of the round robin clock signals in the clock domain of the sending IC. If the phase detection circuit determines that the phase of the select signal has the proper orientation, then the phase detect circuit does not toggle the orientation of the select signal. However, if the phase detection circuit determines that the select signal has an incorrect orientation, then the select signal is delayed for ½ of a cycle of the select signal, thereby establishing the proper orientation of the select signal. Thereafter, the orientation of the select signal remains locked until the system is reset or powered down.
In the scheme disclosed by Rogers, the initial timing of the select signal may be quite close to the point at which the phase detection circuit decides whether to toggle the select signal. As a matter of fact, the system may power-up and toggle the orientation of the select signal one time, and not toggle the orientation the next time the system is powered up. However, this does not cause any problems because when the select signal is locked it will cause the data bit to be read either ¼ or ¾ of the way into the read window. Accordingly, in this situation either orientation of the select signal will produce a valid read.
While the scheme disclosed by Rogers works well, the potential asynchronous nature of the initial determination ofthe orientation of the select signal may cause difficulties when debugging the system. As is known in the art, it is much easier to debug a repeatable problem than it is to debug an intermittent problem. Assume that a system has a hardware bug that only appears with one orientation of the select signal, but not the other. Further assume that the orientation that produces the bug is only selected by the phase detection circuit 1 out of 1000 times the system is powered up. Such a bug will be very hard to isolate.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for forcing synchronous operation in a system that automatically determining a phase-based relationship between two clocks. In accordance with the present invention, a transmitting IC includes a selectable delay capable of delaying data and strobe signals by either one validation edge of the strobe signal, or three validation edges of the strobe signal, or not delaying the data and strobe signals. The sending IC transmits data to a receiving IC over a data bus, and provides the strobe signal, which is delayed by ¼ of a cycle of the internal clock of the sending IC, to validate data at the receiving IC. Because of clock skew, the ¼ cycle delay, and other factors, the phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown.
Within the receiving IC, the strobe signal is used to form four round robin clock signals. Each of the four round robin clock signals has a falling edge once every two cycles of the strobe signal. However, each of the four round robin clock signals is offset from the round robin clock signal logically adjacent to it by ½ of a cycle of the strobe signal. The round robin clock signals are use
Butler Dennis M.
Hewlett--Packard Company
Plettner David A.
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