Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2000-05-10
2003-11-18
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000
Reexamination Certificate
active
06651179
ABSTRACT:
This patent application claims priority based on Japanese patent applications, H11-128665 filed on May 10, 1999 and H11-371468 filed on Dec. 27, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay time judging apparatus which judges the delay time of a delay circuit, and in particular to the delay time judging apparatus which judges a delay path by which an input signal is delayed by a desired amount of time in a variable delay circuit having a plurality of the delay paths.
2. Description of the Related Art
In recent years, semiconductor devices operable at high speeds have been developed with much demand. Complying with such a trend, very severe conditions are put forth on the control of operation timing. In particular, the timing at which a test pattern is input to a semiconductor device under test need be accurately delayed against a reference clock in accordance with the input characteristics of the semiconductor device under test.
FIG. 1
is a block diagram showing a variable delay circuit
10
which delays the input signal by a desired amount of time in a semiconductor testing apparatus. The variable delay circuit
10
includes: delay elements (
12
a,
12
b,
12
c
to
12
n
), selectors (
14
a,
14
b,
14
c
to
14
n
) and a linearization memory
16
. A clock is input from an input terminal, and the delay clock which is delayed by the desired amount of time is output from an output terminal.
The linearization memory
16
stores in a predetermined address the data which specify a delay path by which the input signal is delayed by the desired amount of time. The data on the delay paths indicate combinations of a plurality of delay elements. The selectors (
14
a,
14
b,
14
c
to
14
n
) select either a clock having passed a delay element (
12
a,
12
b,
12
c
to
12
n
) or a clock having not passed the delay element (
12
a,
12
b,
12
c
to
12
n
) based on the delay path data (
160
a,
160
b,
160
c
to
160
n
) provided from the linearization memory
16
, so as to be output to a delay element to follow. For example, when a delay element prior to each selector is used for generating a predetermined delay time, “0” is set to a bit corresponding to the linearization memory
16
while otherwise (i.e., when the delay element is not used) “1” is set.
The delay elements (
12
a,
12
b,
12
c
to
12
n
) provided in the variable delay circuit
10
are so designed that some pico seconds to some tens of pico seconds or some hundreds of pico seconds can be delayed thereby. Thus, in order to generate seven types of delay times (10, 20, 30, 40, 50, 60 and 70 pico seconds), it theoretically suffices to combine three types of delay elements having 10, 20 and 40 pico seconds.
However, there are caused errors between the designed (theoretically calculated) delay time and the actual delay time given by the delay elements, due to irregular quality of the delay elements, temperature conditions at the time of actual use of the delay elements and so on. In order to solve this problem causing the errors, an optimal delay path generating a predetermined delay time need be obtained.
FIG. 2
is a block diagram showing a conventional delay time judging apparatus
48
which measures the delay time of respective delay paths in the variable delay circuit
10
. The delay time judging apparatus
48
includes: a pulse width correcting unit
24
. an OR circuit
25
, a frequency counter
28
and a computer
30
(test controller).
A pulse serving as a measured pulse
132
is input via the OR circuit
25
, so that the pulse rounds a closed circuit comprised of the OR circuit
25
, variable delay circuit
10
and pulse width correcting unit
24
. During the rounding, the measured pulse
32
is delayed by the delay path selected by the variable delay circuit
10
. The pulse width of the measured pulse
132
may decrease or increase due to a difference between the rise time and the fall time of semiconductor gates through which the measured pulse
132
passes during the rounding. Thus, the pulse width correcting unit
24
is provided which corrects the pulse width of the measured pulse
132
. As the delay path changes, the number of rounding during a fixed period of time changes. The frequency counter
28
sends to the computer
30
the difference between a frequency at which the minimum delay path having the minimum delay amount is selected and a frequency at which other delay path than the minimum delay path is selected.
The computer
30
selects a delay path having the closest amount of delay to a predetermined delay time, based on the difference between the frequency at which the minimum delay path is selected and the frequency at which other delay path is selected. The delay path thus selected is stored in the linearization memory
16
.
FIG.
3
A and
FIG. 3B
show data stored in the linearization memory
16
. The linearization memory
16
stores data on the delay path having a desired amount of delay. The data on the delay path are stored in suchawaythat the delay amount increases proportional to the increase of the address of the linearization memory
16
. For example, in the addresses #
0
, #
1
, #
2
, . . . of the linearizatin memory
16
shown in
FIG. 3A
, the data on the delay paths having respectively 0 ps, 10 pcs, 20 ps, . . . are stored. The delay data are proportional to the delay amount as shown in FIG.
3
B. Moreover, the delay time in each delay path is preferably a relative delay time against the delay time in the minimum delay path of the variable delay circuit
10
, instead of an absolute delay time.
The delay time judging apparatus
48
shown in
FIG. 2
measures the amounts of all delay paths that the variable delay circuit
10
has, and then transfers the thus measured delay amount to the computer
30
(tester computer). Thereafter, the data of the delay path which has the closest delay amount to the desired delay time are stored in the linearization memory
16
. Since it takes time to measure the delay amount of respective delay paths, time necessary for correcting the linearization memory
16
increases, thus causing to reduce the throughput.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a delay time judging apparatus and a method therefor which overcome the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to one aspect of the present invention, there is provided a delay time judging apparatus which judges whether or not delay time for delaying an input signal is equal to a desired delay time, the delay time judging apparatus comprising: a shift clock supply unit which supplies a shift clock a phase of which is delayed by the desired delayed time against that of a reference clock; a phase comparing unit which compares a phase of the shift clock to a phase of a delay clock for which the reference clock is delayed by the delay circuit, so as to output a comparison signal; and a judging unit which judges whether or not the delay time of the delay circuit is equal to the desired delay time.
Preferably, the comparison signal is output in a manner that an edge timing of the delay clock is compared to that of the shift clock.
Moreover, the phase comparing unit preferably includes a flip flop having a data input to which the delay clock is input and a clock input to which the shift clock is input.
The phase comparing unit outputs the comparison signal preferably in the form of a pulse.
The judging unit preferably includes: a comparison signal counting unit which outputs a counted value obtained by counting the pulse at a predetermined time interval; and a result judging unit which determines whether or not a phase of the delay clock matches that of the shift clock based on the counted value.
The result judging unit preferably includes a first judgment unit which
Okayasu Toshiyuki
Sato Masatoshi
Sato Shin-ya
Advantest Corporation
Butler Dennis M.
Rosenthal & Osha L.L.P.
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