Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-26
2005-04-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06886152
ABSTRACT:
A delay optimization algorithm has four major steps: (1) selecting signal connections to target for delay improvement; (2) unrouting all signals containing those candidate connections; (3) rerouting those signals, using a “load-balancing”heuristic; and (4) during rip-up and re-try routing, protecting wiring to all signal loads routed by the heuristic, including non-timing critical loads. Load balancing includes (a) applying a branching penalty on logic cell output wire segments, and (b) encouraging all non-route critical loads to route through a single buffered wire segment.
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Hirsch Lorraine S.
Kik Phallaka
Liu Justin
Smith Matthew
Xilinx , Inc.
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