Delay locked loop circuitry for clock delay adjustment

Details Delay locked loop circuitry for clock delay adjustment Delay locked loop circuitry for clock delay adjustment

2000-03-13

2003-03-25

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S358000, C375S373000, C327S158000

Reexamination Certificate

active

06539072

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to clock delay adjustment circuitry. In particular, the present invention relates to the generation of a set of phase vectors and the generation of output clocks that have precise phase relationships to an input clock.
Previous art includes Rambus patent, 5,485,490, Leung and Horowitz, which discloses two independent loops, the first of which creates a fixed number of phase vectors, the second of which creates an output clock that is in phase with the input clock. Also disclosed in this patent is the use of separate circuitry to create a leading phase clock to the output clock by selecting a pair of phase vectors and interpolating between them to produce an output that leads the output clock by the delay between phase vectors available from the first loop.
IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, December 1994, Lee, et. al. (“Lee”) discloses a pair of delay-locked loops (DLL) for transmitting and receiving data in DRAMs. IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, April 1996, Tanoi et al. shows a two-loop architecture in which a frequency locked-loop (FLL) is designed to lock onto an external input frequency and to control the DLL for lock-in to the phase of the external input clock.
It is desirable to improve on the generation of a leading output clock to the in phase output clock. There are several drawbacks to the invention disclosed in U.S. Pat. No. 5,485,490. Phase locked loop circuitry employing a VCO and single order loop filter to create phase vectors is a second order system. This second order system has stability problems associated with its operation. Furthermore, the VCO phase lock loop accumulates phase error in response to sudden change in phase on inputs to the loop, where the input includes not only the input clock but also the power supplies to the loop. This occurs because the loop changes the frequency of the VCO in response to a sudden phase change and this frequency shift is integrated to become phase error which persists for a time on the order of the reciprocal loop bandwidth. (See Lee, above). This causes the loop to be noise sensitive when the noise is in the form of sudden phase shifts. Another drawback regarding the prior art patent is that the subloop used for generating the in-phase clock relies on the accuracy and similarity of a second phase interpolator (out-of-phase phase interpolator) to produce the leading clock. Any lack of matching between the out-of-phase phase interpolator and the in-phase phase interpolator will create a phase error in the desired phase relationship between the leading clock and the in-phase clock. Another drawback concerns the acquisition time of the VCO which can be quite long after restoration of a lost input clock, depending on how long the input clock has been absent.
SUMMARY OF THE INVENTION
The present invention provides delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop (DLL) includes delay elements arranged in a chain, the chain receiving an input clock and generating, from the delay elements, a set of,phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock.
In a preferred embodiment, a second DLL is used, although the second DLL could be used with another circuit which produces two different delayed clock signals. The second DLL selects, from the first DLL, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.
Preferably, a phase detector in the second DLL compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. The phase interpolator is preferably adjusted with a control circuit including a digital memory for storing a count corresponding to the delay adjustment, which can be maintained in the absence of the input clock signal.
Preferably, the first DLL includes a control circuit with a digital memory for providing the desired delay adjustment to the adjustable delay elements. A filter is used between the phase detector and the control circuit to reduce loop jitter.
The present invention is advantageously used for the transmit and receive clocks in high speed DRAM and a high speed DRAM bus channel.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.


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Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”,IEEE Journal of Solid-State Circuits, 29(12):1491-1496 (1994).
Tanoi et al., “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture”,IEEE Journal of Solid-State Circuits, 31(4):487-493 (1996).

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