Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-12
2003-09-30
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S019000
Reexamination Certificate
active
06629299
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a delay library for setting a delay time in a logic cell which is a delay element in a logic circuit, to a method for generating the delay library and to a delay calculation method using the delay library.
Prior art methods will be described with reference to FIGS.
15
(
a
),
15
(
b
) and
16
. As shown in FIG.
15
(
a
), in a prior art method for generating a delay library, an input signal waveform
131
given to an input terminal A of a cell
130
and load capacitance
132
connected to an output terminal Y are put through a circuit simulation using a circuit simulator like SPICE so as to calculate a cell output signal waveform
133
. Based on the input signal waveform
131
and the cell output signal waveform
133
, a cell delay time Td is calculated using the predetermined threshold voltage of the cell
130
. The cell output signal waveform
133
is linear-fitted to calculate a cell output signal waveform
134
. The cell delay time Td and the cell output signal waveform
134
thus calculated are represented in tabular form which uses the input signal waveform
131
and the load capacitance
132
as parameters as shown in FIG.
15
(
b
).
In calculating a cell delay time and a cell output signal waveform using the table shown in FIG.
15
(
b
), when the value of an input signal waveform slew and the value of load capacitance are both shown in the table, the cell delay time and the cell output signal waveform corresponding to these vales are found. If either of these values is not shown in the table, the value of the input signal waveform slew and the value of the load capacitance registered with the table are interpolated to find the cell delay time and the cell output signal waveform.
As shown in
FIG. 16
, another method for calculating a cell output signal waveform is to model the driving ability of the cell by using a NMOS type transistor when the cell output signal waveform falls, and a PMOS type transistor when the waveform rises.
FIG. 16
shows the case where the cell output signal waveform falls.
The signal waveform in an output node
142
which is shaped when a step waveform
143
rising at the time t=0 is entered at the gate terminal
141
of a NMOS type transistor
140
is referred to as the output signal waveform of the cell. When the cell drives a network
144
, the signal waveform in the output node
142
is calculated by connecting the network
144
to the output node
142
, and solving the circuit equation to find the cell output signal waveform.
In a prior art logic simulation method, the propagation delay time of a signal traveling through the gate is represented by a function of either the rise time or the fall time between the, VSS and the VDD of the signal entered at the gate (Refer to Japanese Laid-open Patent Application No. 5-108753). It is possible to represent fluctuations in the delay time affected by the signal waveform, thereby achieving accurate estimation of the delay time.
Problems to be Solved
A prior art delay library is formed on the assumption that the input/output signal waveforms of the cell make a full transition between the power potential VDD and the ground potential VSS. This involves a problem that when a so-called small signal-swing occurs in the actual circuit operation, or when a waveform does not make a full transition between the power potential VDD and the ground potential VSS, the delay time is not calculated accurately.
The prior art logic simulation method requires a signal waveform that makes a full transition between the power potential VDD and the ground potential VSS. Therefore, when the signal waveform fails to make a full transition between the power potential VDD and the ground potential VSS due to high-rate changes of the signal, with improving operating frequency of LSI, there is a problem that the signal potential changes less, thereby shortening the transition time of the signal.
SUMMARY OF THE INVENTION
The present invention has an object of providing a method for representing a delay library which can deal with signal waveforms of small signal-swing and a method for generating the delay library. The present invention has another object of providing a delay calculation method using the delay library.
To be more specific, the present invention discloses a method for representing a delay library used for delay calculation of a cell by assuming that a signal having a first edge and a step waveform which lags the first edge by a fixed time interval, and a signal having a step waveform and a second edge which lags the step waveform by said fixed time interval as an input signal to said cell, and representing a driving ability of said cell either by a function or in a table having as parameters a slew of the first edge, a slew of the second edge, said fixed time interval and load capacitance driven by said cell.
The present invention also disclosed a method for generating a delay library used for delay calculation of a cell, comprising: a first step of finding output signal waveforms of said cell, based on combinations of input signal waveforms and output load capacitances; a second step of determining whether each of the output signal waveforms found in the first step makes a full swing or not; a third step of generating a first delay library from the combinations of the input signal waveforms and output load capacitances concerned with the output signal waveforms that have been determined to make a full swing in the second step; a fourth step of generating a second delay library from the combinations of the input signal waveforms and output load capacitances concerned with the output signal waveforms that have been determined not to make a full swing in the second step; and a fifth step of generating a delay library of said cell by synthesizing the first delay library and the second delay library.
The present invention further discloses a method for calculating a delay time of a cell, comprising: a first step of dividing an input signal waveform having a first edge and a second edge which lags the first edge by a fixed time interval into a first division waveform having the first edge and a step waveform which lags the first edge by said fixed time interval, and a second division waveform having a step waveform and the second edge which lags the step waveform by said fixed time interval, by using said delay library represented by the method of claim 1; a second step of finding, with reference to said delay library, a first output signal waveform which is an output signal waveform shaped when the first division waveform is entered at said cell and a second output signal waveform which is an output signal waveform shaped when the second division waveform is entered at said cell; and a third step of finding an output signal waveform of said cell by synthesizing the first output signal waveform and the second output signal waveform, and said delay time of said cell being calculated based on the input signal waveform, and the output signal waveform found in,the third step.
The present invention further discloses a method for representing a delay library used for delay calculation of a cell by assuming that a signal having a first edge and a second edge which lags the first edge by a fixed time interval is entered as an input signal to said cell, and representing a value of said fixed time interval required for an output signal waveform to make a full swing as a full swing check value when said input signal is entered at said cell either by a function or in a table having as parameters a slew of the first edge and load capacitance driven by said cell.
The present invention further discloses a method for generating a delay library used for delay calculation of a cell, comprising: a first step of finding an output signal waveform of said cell, based on an input signal waveform having a first edge and a second edge which lags the first edge by a fixed time interval, and on output load capacitance; a second step of determining whether the output signal wav
LandOfFree
Delay library representation method, delay library... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Delay library representation method, delay library..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay library representation method, delay library... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3082786