Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2007-11-20
2011-11-01
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S108000, C716S110000, C716S111000, C716S112000, C716S113000, C714S724000, C714S726000, C714S728000, C714S738000, C703S019000
Reexamination Certificate
active
08051403
ABSTRACT:
A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.
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Nozuyama Yasuyuki
Takatori Atsuo
Do Thuan
Fujitsu Semicondoctor Limited
Kabushiki Kaisha Toshiba
Nguyen Nha
Turocy & Watson LLP
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