Delay device, semiconductor testing device, semiconductor...

Details Delay device, semiconductor testing device, semiconductor... Delay device, semiconductor testing device, semiconductor...

1999-11-09

2004-07-27

Decady, Albert (Department: 2816)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

06769082

ABSTRACT:

This patent application claims priority based on a Japanese patent application, H11-067815 filed on Mar. 15, 1999 the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay device, a semiconductor testing device, a semiconductor device, and an oscilloscope and in particular to a delay device, a semiconductor testing device, a semiconductor device, and an oscilloscope provided with an addition circuit that applies a predetermined voltage to a delay element.
2. Description of the Related Art
FIG. 1
shows the delay device D
12
as a related art. The delay device D
12
includes a plurality of delay elements DL in series,with each other. The incoming transmission signal is delayed by each delay element DL producing a delay time of Td.
FIG. 2
shows the current that flows in the delay device D
12
. Once a unit pulse is fed to the delay device D
12
as shown in FIG.
2
(A), the current applied to the delay element DL changes to flow in a burst as shown in FIG.
2
(B). The period of time during which the current flows is equivalent to the delay time Td. When successive pulses are fed to the delay device D
12
as shown in FIG.
2
(C), whilst the initial current generated by the first pulse flows, another current generated by the following pulse also flows, as shown in FIG.
2
(D). When the current of two or more delay elements DL simultaneously changes in this way, the sum of the current flowing in the delay device D
12
changes as shown in FIG.
2
(E). Since the change in the current alters the power supply voltage Vdd and Vss of the delay device D
12
, the accuracy of the delay time Td of the delay device D
12
is decreased.
FIG. 3
shows another delay device D
12
as a related art. The delay device D
12
includes a plurality of selectors SEL in series with each other, and a plurality of delay elements DL each of which delay the incoming transmission signal and feed it to a following selector SEL. The delay element DL has one or more inverters in series with each other. The selector SEL selectively outputs the signal that passes through the delay element DL as well as the signal that does not pass through. The timing of the electric power consumed in the delay device D
12
differs depending upon the selection by the selector SEL. For example, if all the selectors SEL select the outputs of the delay elements DL, the transmission signal advances slowly; accordingly, when the selector SEL closest to the output terminal consumes the electric power, the selector SEL closest to the input terminal also consumes the electric power. That is, the electric power is consumed at two or more selectors SEL. The end result is a reduction in accuracy of delay time because the power supply voltage of the delay device D
12
differs when the electric power is consumed at two or more selectors SEL compared to when consumed at only one selector SEL.
FIG. 4
shows a circuit electrically equivalent to the delay element DL of
FIG. 3. A
wiring capacitance CL arises in the signal line LIN that connects the drive circuit DR and the receipt circuit RC while an input capacitance CG arises at the input terminal of the receipt circuit RC. The input capacitance CG is proportional to the number of receipt circuits RC to be connected, while the wiring capacitance CL is proportional to the length of the signal line LIN. If the input capacitance CG and the wiring capacitance CL are increased, permitting the delay device D
12
to pass the signal requires a larger current. The increase in the current enlarges the change in the current as shown in FIG.
2
(E), thus decreasing the accuracy of the delay time Td.
If the power supply voltage sharply changes due to the operation of the drive circuit DR, an electromagnetic wave noise is radiated. If the change in the power supply current and power supply voltage increases because the signal line LIN is long, the electromagnetic wave noise radiated from the delay device D
10
increases also. The electromagnetic wave noise radiated from the electronic instrument must be below a given level, so it is therefore necessary to prevent the electromagnetic wave noise from arising in the electronic instrument provided with the delay device D
10
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a delay device, a semiconductor testing device, a semiconductor device, and an oscilloscope which overcome the drawbacks in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, there is provided a delay device that delays an incoming transmission signal, comprising: a delay element that operates on the power supply voltages Vdd and Vss thereby delaying the transmission signal, with the voltage Vdd being larger than the voltage Vss; and an addition circuit that outputs to an output of the delay element, a predetermined voltage which is larger than the voltage Vss and smaller than the voltage Vdd.
Preferably, the delay device further comprises a plurality of delay elements in series with each other; and a plurality of addition circuits each connected to one of outputs of the plurality of delay elements. As an additional preference, the delay device further comprises: a switch unit that outputs one of the outputs of the plurality of delay elements, wherein the addition circuit outputs the predetermined voltage to the output of the switch unit.
It is preferable that the delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. The addition circuit should also output a voltage substantially similar to a threshold voltage that the output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.
It is preferable that the addition circuit outputs approximately a midway voltage of the voltage Vss and the voltage Vdd.
It is preferable that the addition circuit has low impedance, smaller than the output impedance of the delay element. More preferably, the output impedance of the addition circuit should range from half to a quarter of the output impedance of the delay element.
It is preferable that the addition circuit includes a first logical gate that inversely outputs an input signal, and a feedback circuit that connects an input terminal of the first logical gate and an output terminal thereof. More preferably, the delay element may include a second logical gate, with the first logical gate having a ratio substantially similar to a ratio of the second logical gate. Similarly, and more preferably, the first logical gate includes one inverter, a NAND gate, and a NOR gate. Similarly, more preferably, the delay element includes a second inverter, with the inverter having a ratio substantially similar to the ratio of the second inverter.
Preferably, the delay device further comprises: a plurality of delay elements in series with each other, and a selector that selects from among the plurality of delay elements one to which the transmission signal is input. The addition circuit outputs a predetermined voltage in response to the input transmission signal which is larger than the voltage Vss and smaller than the voltage Vdd.
Preferably, the delay device further comprises: a plurality of capacitors that store the electric charge of the transmission signal output by the delay element; and a plurality of switches that switch the plurality of capacitors to the output of the delay element. It is more preferable that the capacitor includes the following: a P-type FET where voltage Vdd is applied to a gate of the P-type FET, while at least one of a drain and a source of the P-type FET is connected to the gate, and another thereof is connected to the switch; an N-type FET where the voltage Vss is applied to a gate of the N-type FET, while at least one of a drain and a source of

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