Defective address storage scheme for memory device

Details Defective address storage scheme for memory device Defective address storage scheme for memory device

2001-09-28

2003-04-08

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06545920

ABSTRACT:

This application claims priority from Korean patent application No. 2000-69533 filed Nov. 22, 2000 which is incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a scheme for storing an address of a defective memory cell.
2. Description of the Related Art
For many integrated circuit memory arrays, several redundant rows or columns are provided to be used as substitutes for defective rows or columns of main memory cells. When a defective row or column is identified, rather than treating the entire chip as defective, a redundant row or column can be employed instead of the defective row or column. The redundant row or column corresponding to the defective row or column is assigned for replacing the defective row or column. Then, when an address corresponding to the defective row or column is provided, the redundant row or column is accessed instead.
For the purpose of replacing the defective row or column with the redundant row or column, the memory device includes a defective address storage circuit (or, defective address detection circuit). The defective address storage circuit monitors row/column addresses and enables the redundant row or column in place of the defect row or column when the defective row or column address is provided. Some defective address storage circuits are disclosed in U.S. Pat. No. 5,258,953 entitled “Semiconductor Memory Device”, U.S. Pat. No. 5,657,280 entitled “Defective Cell Repairing Circuit and Method of Semiconductor Memory Device”, and U.S. Pat. No. 5,723,999 entitled “Redundant Row Fuse Bank Circuit”.
FIG. 1
is a circuit diagram showing a prior art defective address storage circuit. The circuit of
FIG. 1
includes a fuse
11
, P-channel metal oxide semiconductor (MOS) transistor
12
, inverter
13
, and NOR-type fuse bank (or, NOR-type fuse array)
30
. The fuse
11
and the PMOS transistor
12
are connected between a power supply voltage and a node NO, and the PMOS transistor
12
is switched on/off in response to a signal nRchk. An input terminal of the inverter
13
is connected to node NO, and an output terminal thereof provides a signal nRcen. The NOR-type fuse bank
30
includes fuses
14
through
24
, and N-channel MOS transistors
15
~
25
which correspond to fuses
14
through
24
, respectively. As shown in
FIG. 1
, the fuses
14
~
24
and the NMOS transistors
15
~
25
are arranged in a NOR architecture.
If no defective cells are identified, fuse
11
is blown and fuses
14
~
24
of the fuse bank
30
remain connected. In this state, at least one of the NMOS transistors
15
~
25
is turned on regardless of the combination of address signals A
0
, nA
0
, A
1
, nA
1
, A
2
, and nA
2
provided, so the signal at node N
0
remains low.
If, however, a defective row or column is identified, fuse
11
is left in the connected state, and fuses
14
~
24
of the fuse bank
30
are selectively cut to detect the address corresponding to the defective row or column. For example, if the address of a defective row or column is indicated by address signals A
0
~A
2
being low, then fuses
14
,
18
, and
22
are left connected, while fuses
16
,
20
, and
24
are cut. Thus, when address signals A
0
~A
2
are low (and address signals nA
0
~nA
2
are high), node NO is charged to the high level through fuse
11
and PMOS transistor
12
because all current paths from node NO to ground are cut off. The signal nRcen is driven low by the inverter
13
, which indicates that the row or column of the current address has a defect.
The signal nRcen causes the defective row or column to be replaced with the corresponding redundant row or column. When address signals corresponding to a normal row or column are provided, at least one of the address signals A
0
~A
2
is high, so the NMOS transistor corresponding thereto is turned on. Thus, a current path is created from node N
0
to the ground voltage terminal. Since the current drive capability of the PMOS transistor
12
is set lower than that of the NMOS transistors of the fuse bank
30
, the node N
0
is maintained at the low level, thereby causing the signal nRcen to go high.
Memory devices typically include multiple defective address storage circuits. As described above, each of the defective address storage circuits creates a direct current path from the power supply voltage to the ground voltage when the address provided from the outside is not identical with the stored address of the defective address storage circuit. This results in unnecessary current consumption.
SUMMARY OF THE INVENTION
The present invention involves the use of address storage blocks coupled in series to reduce current consumption in a defective address storage circuit for a semiconductor memory device.
One aspect of the present invention is a defective address storage circuit for a semiconductor memory device having redundant cells for replacing defective memory cells, the circuit comprising: a precharge circuit coupled between a first voltage terminal and an output node and adapted to precharge the output node to a potential of the first voltage terminal in response to a control signal; and a fuse bank coupled between the output node and a second voltage terminal and adapted to store address signals corresponding to a defective memory cell; wherein the fuse bank comprises address storage blocks coupled in series between the output node and the second voltage terminal.
Another aspect of the present invention is a defective address storage circuit for a semiconductor memory device comprising a plurality of address storage blocks coupled in series.
A further aspect of the present invention is a defective address storage circuit for a semiconductor memory device comprising: means for precharging an output node; and a plurality of means for storing a defective address coupled in series with the output node.


REFERENCES:
patent: 5258947 (1993-11-01), Sourgen
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5657280 (1997-08-01), Shin et al.
patent: 5723999 (1998-03-01), Merritt
patent: 5822257 (1998-10-01), Ogawa
patent: 5995422 (1999-11-01), Im et al.

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