Defect localization based on defective cell diagnosis

Details Defect localization based on defective cell diagnosis Defect localization based on defective cell diagnosis

2007-10-22

2010-11-16

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S724000, C714S729000, C714S737000, C714S742000, C324S528000, C324S531000, C324S537000, C324S765010, C702S117000

Reexamination Certificate

active

07836366

ABSTRACT:
Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.

REFERENCES:
patent: 6708306 (2004-03-01), Bartenstein et al.
patent: 7051253 (2006-05-01), Rooney et al.
patent: 7441168 (2008-10-01), Yoshida et al.
patent: 7594206 (2009-09-01), Yoshida et al.
patent: 2006/0053357 (2006-03-01), Rajski et al.
patent: 2006/0111873 (2006-05-01), Huang
patent: 2007/0100586 (2007-05-01), Cheng et al.
patent: 2008/0250284 (2008-10-01), Guo et al.
Desineni et al., Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction, 2005, IEEE, pp. 1-8.
Desineni et al., A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior, Oct. 22-27, 2006, IEEE, paper 12.3, pp. 1-10.
Mohammad et al., Fault Models and Test Procedures for Flash Memory Disturbances,Aug. 3, 2001, Kluwer Academic Publishers, pp. 495-508.
Li et al., Diagnosis of Resistive-Open and Stuck-Open Defects in Digital CMOS ICs, Nov. 2005, IEEE, vol. 24, No. 11, pp. 1748-1759.
Abramovici et al.,Digital Systems Testing and Testable Design, IEEE Press, pp. 226-227, 234-240 (1990).
Amyeen et al., “Improving Precision Using Mixed-Level Fault Diagnosis,” inProc. ITC, pp. 1-10 (Oct. 2006).
Bartenstein et al., “Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm,”Proc. ITC, pp. 287-296 (2001).
Blanton et al., “Fault Tuples in Diagnosis of Deep-Submicron Circuits,”Proc. ITC, pp. 233-241 (2002).
Desineni et al., “A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior,”Proc. ITC, pp. 1-10 (Oct. 2006).
Fan et al., “A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis,”IEEE VLSI Test Symp., pp. 266-271 (Apr. 30-May 4, 2006).
Fan et al., “A Novel Stuck-at Based Method for Transistor Stuck-Open Fault Diagnosis,”Proc. ITC, pp. 253-262 (Nov. 8-10, 2005).
Guo et al., “An Algorithmic Technique for Diagnosis of Faulty Scan Chains,”IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, No. 9, pp. 1861-1868 (Sep. 2006).
Higami et al., “Diagnosis of Transistor Shorts in Logic Test Environment,”Proc. Asian Test Symp., pp. 354-359 (Nov. 2006).
Hirase et al., “Scan chain diagnosis using IDDQ current measurement,”Proc. Design Automation and Test in Europe, pp. 1302-1307 (2004).
Huang et al., “Compressed Pattern Diagnosis for Scan Chain Failures,”Proc. ITC, pp. 744-751 (Nov. 8-10, 2005).
Lavo, “Multiplets, Models and the Search for Meaning: Improving Per-Test Fault Diagnosis,”Proc. ITC, pp. 250-259 (2002).
Leininger et al., “Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes,”IEEE, 6 pp. (2004).
Pomeranz et al., “Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults,”Proc. VLSI Design, pp. 475-480 (2004).
Rajski et al., “Embedded Deterministic Test,”IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 5, pp. 776-792 (May 2004).
Sharma et al., “Faster Defect Localization in Nanometer Technology based on Defective Cell Diagnosis,”Proc. ITC, pp. 1-10 (Oct. 21-26, 2007).
Venkataraman et al., “POIROT: A Logic Fault Diagnosis Tool and Its Applications,” Proc.ITC, pp. 253-262 (2000).
Waicukauski et al., “Failure Diagnosis of Structured VLSI,”IEEE Design and Test of Computers, pp. 49-60 (Aug. 1989).
Wen et al., “Fault Diagnosis for Static CMOS Circuits,”Proc. Asian Test Symposium, pp. 282-287 (1997).
Zou et al., “On Methods to Improve Location Based Logic Diagnosis,”Proc. VLSI Design, pp. 181-187 (Jan. 3-6, 2006).

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